Code Coverage in Verification..IMP

Discussion in 'VHDL' started by Abs, Mar 6, 2006.

  1. Abs

    Abs Guest

    hi,
    i need to clear some doubts out here, n i hope the brains out here come
    of real help, n thanks in advance,
    well my doubt is, i have to verify VHDL designs (codes written in
    VHDl/VERILOG), to do so, i need to write a TCL Script, and do
    functionality testing which is over. NOw to proceed with testing each
    line, step by step, is it possible to do in TCL Script, like using the
    command "STEP". To check for buggs free code, to check for all the
    cases, all teh loops, every statement in a code is executed or not, i
    have to do Code Coverage. So my actual doubt is is code coverage a part
    of TCL Script or a Tool used to check the correctness of a design and
    is a part of verification. Should i provide inputs, rare input data,
    and check for this input any case staement is left unexecuted, or of
    the same kind. To write TCL Script and to carry on Code Coverage i'am
    using MOdelSIm PE. i hope i have made things clear and lucid.

    THANK YOU VERY MUCH..

    And i guess, many people around will ahev the same problem, and lets
    just get it better for every1 out here..

    REGARDS...
     
    Abs, Mar 6, 2006
    #1
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  2. Hi,

    Abs schrieb:
    > well my doubt is, i have to verify VHDL designs (codes written in
    > VHDl/VERILOG), to do so, i need to write a TCL Script, and do
    > functionality testing which is over. NOw to proceed with testing each
    > line, step by step, is it possible to do in TCL Script, like using the
    > command "STEP". To check for buggs free code, to check for all the
    > cases, all teh loops, every statement in a code is executed or not, i
    > have to do Code Coverage. So my actual doubt is is code coverage a part
    > of TCL Script or a Tool used to check the correctness of a design and
    > is a part of verification.


    Code coverage is a metric. The tool "code coverage" allows you to say
    something about the quality of your tests. But the code coverage alone
    won't help you in testing a design.

    You can use the modelsim code coverage (stm, branch, toggle,..) to
    learn which parts of your code are executed and where you need to
    extend test cases in order to execute each statement.
    You should be aware, the number alone has nothing to say without
    understanding how to use code coverage. 100% Coverage means, that
    everything is executed, _not_ that everything is tested. A module with
    active inputs and inactive outputs is easy executed, but hardly tested.


    bye Thomas
     
    Thomas Stanka, Mar 6, 2006
    #2
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  3. Abs

    Abs Guest

    hi,
    thanks, got some of it. understood most of it.
    so how do i give the inputs, i have a test vector, for which i want to
    test wheather all teh statements are executed well, i get 99%, how do i
    provide the input vector. should i use TCL Script or Testbenches. There
    are commands actually used to do code/state/branch coverage, are those
    TCL commands. should i write a TCL Script to do all that.
    Please clear my doubt.

    Thanks
     
    Abs, Mar 6, 2006
    #3
  4. Abs wrote:

    > so how do i give the inputs, i have a test vector, for which i want to
    > test wheather all teh statements are executed well, i get 99%, how do i
    > provide the input vector. should i use TCL Script or Testbenches.


    I prefer to use a procedural vhdl testbench to
    provide stimulus and verification, like the one here:
    http://home.comcast.net/~mike_treseler/

    > There
    > are commands actually used to do code/state/branch coverage, are those
    > TCL commands. should i write a TCL Script to do all that.


    Coverage is icing on the cake.
    You need cake first.
    Modelsim SE has an automatic interface to do coverage
    testing for you, once you have working uut and testbench code.

    -- Mike Treseler
     
    Mike Treseler, Mar 6, 2006
    #4
  5. Abs

    Ajeetha Guest

    Hi,
    You are mixing several things here. Stimulus generation, debugging,
    progress monitoring and checking.

    Stimulus generation - best handled via testbenches in HDL/HDVL etc. TCL
    is OK for small designs

    Debugging - is where you use STEP etc.

    Progr. Monitor - This is what code coverage does for you.

    Checking - often the tougher part, best done using HDL/HDVL/HVL or some
    golden reference models.

    Regards
    Ajeetha
    www.noveldv.com
     
    Ajeetha, Mar 7, 2006
    #5
  6. Abs

    Abs Guest

    hi..
    thanks to you 2. i have developed a testbench, simulated the design and
    got a coverage report for the same. i have written a testbench for it,
    and have to attain close to 99% for a good performance. It all depends
    on how well the testbench has been written. i should provide input to
    the design so max portion of the design to be executed.
    I'am using modelsim PE. is this a good tool for this application.

    Thanks agian for your sincere help..
    cheers!!
     
    Abs, Mar 7, 2006
    #6
  7. Abs

    Abs Guest

    i have one more doubt, i have to write just one testbench that should
    get max coverage that can be obtained. so i need just one testbench and
    should be well written.so it covers all the possible input values.
     
    Abs, Mar 7, 2006
    #7
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