combinational logic in reference design

Discussion in 'VHDL' started by Mike Treseler, Mar 1, 2007.

  1. Marcin Wójcik wrote:
    >
    > I've started using your design methodology (init_regs etc.) some time

    ago. I have got a question related to this. It is possible to describe
    "pure" combinational logic in combination with this design method? I
    tried to implement some amba arbiter and decoder in one process, decoder
    is combinational, arbiter is not. I implemented it in 2 process, one
    using (init_regs etc.) and second only combinational. I wonder if it is
    possible to do this using only one process with structure that you
    proposed. I've tried to describe some combinational logic in
    update_ports procedure but (I think) it's not the good way.
    >
    > Marcin Wojcik
    >

    If the logic were purely combinational from device pin to device pin,
    I would put it in a separate entity to be instanced in the top level.

    If the output were a combinational function of register variables to
    a device pin, I would put the assignment in the update_ports procedure
    between the END IF and END PROCESS.

    If the "output" were between two processes,
    I would combine the processes into one.

    -- Mike Treseler
    Mike Treseler, Mar 1, 2007
    #1
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