combinationel loop

F

fpga.vhdl.designer

hi,

i wrote this
FROZE_LAMBDA : process(clock,frozen,lambda_PE)
variable flag : std_logic;
begin
if frozen='0' then
flag := '0';
lambda_in <= lambda_PE;
elsif (clock'event and clock='1') then
if data_en='1' then
if flag = '0' then
lambda_in <= lambda_PE;
flag := '1';
end if;
end if;
end if;
end process FROZE_LAMBDA;

I've got this message from Quartus 6.0 timing analyser..
Warning: Timing Analysis is analyzing one or more combinational loops
as latches on lambda_in

I want lambda_in taken the value on frozen='0' and (data_en=1 and
flag='0') and to be frozen for others cases...

I don't have the warning under Cyclone I and now on Cyclone II I've
got this new warning

how to get out this warning ?

thanks
 
F

fpga.vhdl.designer

and I have too the frozen signal detected as :
Warning: Found 1 node(s) in clock paths which may be acting as ripple
and/or gated clocks -- node(s) analyzed as buffer(s) resulting in
clock skew, frozen as buffer !!!

my frozen signal is a register ouptut !!

why quartus see it as as a clock, I use it only in the process above
where frozen is a asynchronous reset !!
 
F

fpga.vhdl.designer

I have found myself... with syncrhounous reset.. and the design works
always...

if (clock'event and clock='1') then
if frozen='0' then
lambda_in <= lambda_PE;
flag := '0';
elsif data_en='1' then
if flag='0' then
lambda_in <= lambda_PE;
flag := '1';
end if;
end if;
end if;
 
J

Jan Zegers

hi,

i wrote this
FROZE_LAMBDA : process(clock,frozen,lambda_PE)
variable flag : std_logic;
begin
if frozen='0' then
flag := '0';
lambda_in <= lambda_PE;
elsif (clock'event and clock='1') then
if data_en='1' then
if flag = '0' then
lambda_in <= lambda_PE;
flag := '1';
end if;
end if;
end if;
end process FROZE_LAMBDA;

I've got this message from Quartus 6.0 timing analyser..
Warning: Timing Analysis is analyzing one or more combinational loops
as latches on lambda_in

I want lambda_in taken the value on frozen='0' and (data_en=1 and
flag='0') and to be frozen for others cases...

I don't have the warning under Cyclone I and now on Cyclone II I've
got this new warning

how to get out this warning ?

thanks

I believe the problem could come from the async reset
using a value lambda_PE instead of a constant. Since
we don't see the complete code, we can't be sure.

Could you try to async reset lambda_in to '0' e.g.
and test it again?

Kind regards,
Jan
 
F

fpga.vhdl.designer

yes effectively if I let the asynchronous reset and put 0 in lamda_in

all the warnings disapear and I have a correct Fmax espected...
 
F

fpga.vhdl.designer

if frozen='0' then
flag := '0';
for I in 0 to (NB_BLOCS/2) loop
lambda_in_1(I) <= (others=>'0');
end loop;
elsif rising_edge (clock) then
if data_en='1' then
if flag='0' then
lambda_in_1 <= lambda_PE;
flag := '1';
end if;
end if;
end if;
end process FROZE_LAMBDA;

with frozen select
lambda_in <=
lambda_PE when '0',
lambda_in_1 when '1',
lambda_PE when others;

this version works perfectly and have the good Fmax

thanks... to your help
 

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