Problem to compile vhdl code

[Cell]

Hi all! Iam having a problem to compile my vhdl code in quartus II, it just stuck and I have to end task. If someone find the problem in the code below, I would be thankful.

Some points: Im brazilian, so some words are in portuguese. Its just a semaphore (semaforo) that have some time to change colors. I could just put some delay and change output, but I have to do this using fsm. The clock is set to 1hz, so T=1s per clock. Verm=red color, amar=yellow color and verde=green color.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity semaforo is
port (clock,resetn: in std_logic;
verm,amar,verde: out std_logic);
end;

architecture circuito of semaforo is

type estado is (red,yellow,green);
signal atual,proximo: estado;

begin

process (clock,resetn)
begin
if (resetn='0') then
atual<=red; --begin in red color
elsif (clock'event and clock='1') then
atual<=proximo; --actual receive next
end if;
end process;

process (atual)
variable count: integer:=0;
begin
case (atual) is
when red =>
verm<='1';
amar<='0';
verde<='0';
--wait for 5sec; it would works if wasnt process sensitive
--proximo<=green;
count:=0;
while (count<5) loop
IF (clock'event and clock='1') then
count:=count+1;
end if;
end loop;
if (count=5) then
proximo<=green;
else
proximo<=atual;
end if;

when green =>
verm<='0';
amar<='0';
verde<='1';
count:=0;
while (count<7) loop
IF (clock'event and clock='1') then
count:=count+1;
end if;
end loop;
if (count=7) then
proximo<=yellow;
else
proximo<=atual;
end if;

when yellow =>
verm<='0';
amar<='1';
verde<='0';
count:=0;
while (count<2) loop
IF (clock'event and clock='1') then
count:=count+1;
end if;
end loop;
if (count=2) then
proximo<=red;
else
proximo<=atual;
end if;
end case;
end process;
end circuito;


When I put loop off it works (not works, just compile)

 

[joris]

- You didn't make the second process sensitive to the clock (so simulation results will probably be wrong)

- You probably need to use the standard idiom for a sequential process for the second process -- that, or move out all clock related statements to the first process;

 

[Cell]

- You didn't make the second process sensitive to the clock (so simulation results will probably be wrong)

If I put the second process sensitive to the clock, it wont work wrongly? I mean, both will work at same time like:

elsif (clock'event and clock='1') then
atual<=proximo; --actual receive next

so atual could receive proximo before the status proximo to update

- You probably need to use the standard idiom for a sequential process for the second process -- that, or move out all clock related statements to the first process;

I dont see any problems in using my idiom because they are just names
if I use just one process, it would work?

Thank you for reply me joris!

 

[joris]

You are using clock'event inside the second process, but that one really looks like you meant to be combinatorial, not sequential;

You are doing this:

while (count<5) loop
IF (clock'event and clock='1') then
count:=count+1;
end if;
end loop;

That is very unusual to have a rising edge-sensitive block in a while loop -- I think that's wrong really.

You might go to a one-process solution; Another way (more similar to what your code looks like currently) is only moving the counting into the sequential part.

I think this comes closer to what you meant: (though it needs some testing)

architecture circuito of semaforo is

type estado is (red,yellow,green);
signal atual,proximo: estado;
[B]signal count, nextCount: integer;[/B]
begin

process (clock,resetn)
begin
if (resetn='0') then
atual<=red; --begin in red color
[B]count<=-1; -- incrementing it leads to (red,0) state
-- an alternative would be starting with (yellow,2)[/B]
elsif (rising_edge(clock)) then
atual<=proximo; --actual receive next
[B]count<=nextCount;[/B]
end if;
end process;

process (atual,count)
begin
case (atual) is
when red =>
verm<='1';
amar<='0';
verde<='0';

if (count=5) then
proximo<=green;
[B]nextCount <= 0;[/B]
else
proximo<=atual;
[b]nextCount <= count + 1;[/b]
end if;

when green =>
verm<='0';
amar<='0';
verde<='1';

if (count=7) then
proximo<=yellow;
[b]nextCount <= 0;[/b]
else
proximo<=atual;
[b]nextCount <= count + 1;[/b]
end if;

when yellow =>
verm<='0';
amar<='1';
verde<='0';

if (count=2) then
proximo<=red;
[b]nextCount <= 0;[/b]
else
proximo<=atual;
[b]nextCount <= count + 1;[/b]
end if;

end case;

end process;
end circuito;

Also note that a range for count (and nextCount) should be defined -- otherwise the full range of a 32-bit integer is used, which obviously is not what you need here.

 

[Cell]

Joris as soon as possible I will try to change the program and post the results! Thanks anyway.
Obs: Someone suggests some good material about vhdl? I just learned using, and I think Im missing to much points. Some tips about material of microprocessors and microcontrollers (like pic) would be interessant to my next semester on university.