Y
YesMann
Hello,
I have error in the process below;
My process is:
1. process(cycle)
2. begin
3. case cycle is
4.
5.
6. WHEN "000000" | "000001" | "000010" => REG <= "001000";
7. WHEN "000011" to "011101" => REG <= "000000";
8. WHEN "011110" | "011111" | "100000" => REG <= "001010";
9. WHEN "100001" => REG <=
"000010";
10. WHEN "100010" | "100011" | "100100" => REG <= "001101";
11. WHEN "100101" to "101000" => REG <= "000101";
12.
13. WHEN OTHERS => REG <="000000";
14.
15. end case;
16. end process;
The line 7 and 11 are considered as error : " Range must be a scalar type".
What can I specified the range "000011" to "011101" in VHDL language ?
Thanks in advance
I have error in the process below;
My process is:
1. process(cycle)
2. begin
3. case cycle is
4.
5.
6. WHEN "000000" | "000001" | "000010" => REG <= "001000";
7. WHEN "000011" to "011101" => REG <= "000000";
8. WHEN "011110" | "011111" | "100000" => REG <= "001010";
9. WHEN "100001" => REG <=
"000010";
10. WHEN "100010" | "100011" | "100100" => REG <= "001101";
11. WHEN "100101" to "101000" => REG <= "000101";
12.
13. WHEN OTHERS => REG <="000000";
14.
15. end case;
16. end process;
The line 7 and 11 are considered as error : " Range must be a scalar type".
What can I specified the range "000011" to "011101" in VHDL language ?
Thanks in advance