constrained random verification of a fifo - with OSVVM

Discussion in 'VHDL' started by alb, Dec 6, 2013.

  1. alb

    alb Guest

    Hi everyone,

    I have an 'event fifo' which is a fifo storing packages of data upon a
    'trigger' condition on one side, while a serial interface is pulling
    events out on the other.

    Through the serial interface I may not only pull out events but also
    monitor a status register with some status bits of the fifo itself
    (full, empty, almost-full, almost-empty).

    My goal is to verify that the fifo runs correctly in all conditions and
    the appropriate level of handshake in the system is capable to handle a
    fifo-full condition.

    My 'simulation framework' has an harness and several testcases (for
    different purposes), together with other entities that appropriately
    stimulate each interface to the logic. One such an entity is the
    'trigger', which initiate the various 'trigger conditions' upon a
    transaction from my testcase:

    <code: testcase.vhd>
    while number_of_loops > 0 loop
    -- use number_of_loops as a seed for random trigger pattern
    generate_trigger_pattern(number_of_loops);
    -- initiate transaction to set the trigger pattern
    set_trigger_pattern(data, to_srv, fr_srv);
    -- verify data packet polling through serial port
    -- ...

    number_of_loops := number_of_loops - 1;
    end loop;
    </code: testcase.vhd>

    Now as you can see above (hopefully my snapshot is not too cryptic), I
    have a very 'sequential' approach, where each trigger condition is
    followed by a poll of an event, so I can never run with more than one
    event in my fifo. My plan therefore is to change the transaction for the
    trigger module in a way that it will start initiating trigger conditions
    by itself concurrently and at a randomly distributed pace.

    But now it comes the problem of 'coverage'. How may I define my bins and
    my coverage model?

    I believe that my randomization variables should somehow affect the
    speed at which the trigger module generates trigger patterns on one
    side, and the speed of polling events on the other, so some sort of
    cross-coverage I guess?

    In the subject I specified OSVVM because that is what I'd like to use in
    the first place. I'm not willing at this time to dig into SV UVM since I
    have not enough time to learn another language and also because I
    strongly support the rise of OSVVM ;-).

    Any suggestion/remark/pointer would be greatly appreciated and yes I
    wish one day I can take the testbench course from SynthWorks but my
    current schedule is still very packed. Hopefully one day...

    Thank you all,

    Al

    --
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    alb, Dec 6, 2013
    #1
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  2. alb

    Jim Lewis Guest

    Hi Al,
    In this case, ad-hoc functional coverage will work well. What you want to detect is a write attempt while the FIFO is full and a read attempt while the FIFO is empty. You can capture each of these at the active edge of clock with a single assignment. Next you need to count each of the attempts. I count each of these as they rise (again with a single conditional assignment).

    That should take care of your coverage modeling. As for the random traffic, I do random bursts with random idle times separating them on both the TX and RX side. Make sure that the testbench TX and RX can run independently from each other - ie: are in separate processes.

    Jim
    Jim Lewis, Dec 6, 2013
    #2
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