convert variables into signal

Discussion in 'VHDL' started by vasim98, Aug 7, 2006.

  1. vasim98

    vasim98

    Joined:
    Jun 27, 2006
    Messages:
    4
    Hi all
    What are the rules to convert variables into signals in a given VHDL RTL description so that the behavior of the circuit remains same?


    Please comment

    Thanks
    vasim98, Aug 7, 2006
    #1
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