converting bitvector to integer

[Xin Xiao]

I want to convert a bit_vector to an unsigned integer, using function
to_integer, from ieee.

variable Ain : bit_vector(15 downto 0);

addr := to_integer(unsigned(Ain));

The error is "The expression can not be converted to type unsigned".

I've included use IEEE.NUMERIC_STD.ALL in the header.

any suggestions?

 

[Mike Treseler]

I want to convert a bit_vector to an unsigned integer, using function
to_integer, from ieee.

addr := to_integer(unsigned(to_stdlogicvector(Ain)));

 

[Xin Xiao]

now the error is "to_integer can not have such operands in this context"

 

[KJ]

now the error is "to_integer can not have such operands in this context"

Your original post defined Ain as a bit vector even though you said you were
trying to covert a bit vector to an unsigned integer.

From OP: variable Ain : bit_vector(15 downto 0);

Change the definition of Ain to

variable Ain: natural range 0 to 65535;
or
variable Ain: integer range 0 to 65535;

KJ

 

[Mike Treseler]

In that case, Ain is not a bit_vector after all.
See the sim example below for that conversion.
Consider using numeric_std.unsigned
or natural directly as KJ suggests.

-- Mike Treseler
________________________________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bitvector is
end entity;

architecture sim of bitvector is
begin
one : process is
variable Ain : bit_vector(15 downto 0) := x"0003";
variable addr : natural;
begin -- process
addr := to_integer(unsigned(to_stdLogicVector(Ain)));
if addr = 3 then
report "Pass";
else
report "Error";
end if;
wait;
end process one;
end architecture sim;

--# vsim -c bitvector
--# Loading work.bitvector(sim)
--VSIM 1> run
--# ** Note: Pass
--# Time: 0 ns Iteration: 0 Instance: /bitvector
--VSIM 2>

 

[Xin Xiao]

i solved my problem, see http://www.xilinx.com/support/answers/23309.htm

 

[KJ]

In that case, Ain is not a bit_vector after all.
See the sim example below for that conversion.
Consider using numeric_std.unsigned
or natural directly as KJ suggests.

Actually, KJ was having trouble reading after the Christmas nog or
something.

I was trying to get across that 'addr' (not Ain) was possibly not of the
correct type which could also cause the error. Xin's post did not specify
what 'addr' is...and it all went downhill from there.

KJ

 

[KJ]

i solved my problem, see http://www.xilinx.com/support/answers/23309.htm

(From the xilinx post)

To work around the problem:
- Replace "TO_INTEGER" with "conv_integer" in des.vhd; synthesis with XST
will finish.
- Place "use IEEE.Std_logic_arith.all;" after "use IEEE.numeric_std.all;".

This problem is fixed in ISE 9.1i.

Gag...

KJ

 

[Mike Treseler]

(From the xilinx post)

To work around the problem:
- Replace "TO_INTEGER" with "conv_integer" in des.vhd; synthesis with XST
will finish.
- Place "use IEEE.Std_logic_arith.all;" after "use IEEE.numeric_std.all;".

Pass me some of that nog
That's a superior work-around.

-- Mike Treseler

 

[Andy]

I want to convert a bit_vector to an unsigned integer, using function
to_integer, from ieee.

variable Ain : bit_vector(15 downto 0);

addr := to_integer(unsigned(Ain));

The error is "The expression can not be converted to type unsigned".

I've included use IEEE.NUMERIC_STD.ALL in the header.

any suggestions?

use ieee.numeric_bit.all;

It defines signed and unsigned as arrays of bit, instead of arrays of
std_logic.

Andy