Converting 'flat' gate level names to hierarchical names

[Paddy McCarthy]

I have an hierarchical RTL design that is synthesised, placed and
routed to generate a flat gate level representation. tools exist that
can show that the
RTL and gate level netlists are functionally equivalent.

When simulating the gates I want the option of probing and viewing
some
signals as they would appear in the RTL.
Theoretically all the RTL signals should either appear in the gates or
be
derivable from other signals in the gate level netlist using boolean
functions
for synchronous parts of the design.

Most waveform browsers allow you to display traces that are a function
of other signals allowing signals to be reconstructed.

What I cannot find is a tool that would do the reconstruction of, for
example,
all the I/O including busses, of an entity/module described in RTL
terms, but
on the gate level simulation.

Notice that I don't want to restrict the synthesis or P&R steps by
asking them to preserve some hierarchy as this would adversely affect
their results.

I guess that the question is: Is their such a tool available?

A way that one could be built is maybe as an additional option to
equivalence checkers, where you could list the RTL signals you want to
probe
and have the tool auto-generate simulator and waveform browser scripts
to
recreate the signals & busses from the gate-level netlist.

What do you think?

Pad.

 

[Anthony J Bybell]

A way that one could be built is maybe as an additional option to
equivalence checkers, where you could list the RTL signals you want to
probe
and have the tool auto-generate simulator and waveform browser scripts
to
recreate the signals & busses from the gate-level netlist.

What do you think?

Not exactly an answer to you, but to the gtkwave users out there:

gtkwave can do this automatically if the dumping order is sane. (If
you ever saw a signal name with a square box next to it this to work
in the browser, that indicated that they were autocoalesced.) Anyway,
related signals need to be dumped with consecutive $var..$end
directives having a common prefix: a[2], a[1], a[0]. If your
simulator doesn't do this, it could be done externally by sorting the
$var lines with a special alphanumeric sort routine that preserves the
numerical values so that 1 < 2 < 10 then by reinserting the lines in
question.

If nets are specified flat earth style it shouldn't matter though you
may need to set alt_hier_delimeter in your .gtkwaverc file if other
characters like '/' are used to specify a change in hierarchy.

-t

p.s.: an example of such a sort routine follows, taken from gtkwave's
bitvec.c:

int sigcmp(char *s1, char *s2)
{
unsigned char c1, c2;
int u1, u2;

for(;
{
c1=(unsigned char)*(s1++);
c2=(unsigned char)*(s2++);

if((!c1)&&(!c2)) return(0);
if((c1<='9')&&(c2<='9')&&(c2>='0')&&(c1>='0'))
{
u1=(int)(c1&15);
u2=(int)(c2&15);

while(((c2=(unsigned char)*s2)>='0')&&(c2<='9'))
{
u2*=10;
u2+=(unsigned int)(c2&15);
s2++;
}

while(((c2=(unsigned char)*s1)>='0')&&(c2<='9'))
{
u1*=10;
u1+=(unsigned int)(c2&15);
s1++;
}

if(u1==u2) continue;
else return((int)u1-(int)u2);
}
else
{
if(c1!=c2) return((int)c1-(int)c2);
}
}
}

 

[Paddy McCarthy]

A way that one could be built is maybe as an additional option to
equivalence checkers, where you could list the RTL signals you want to
probe
and have the tool auto-generate simulator and waveform browser scripts
to
recreate the signals & busses from the gate-level netlist.

What do you think?

Not exactly an answer to you, but to the gtkwave users out there:

gtkwave can do this automatically if the dumping order is sane. (If
you ever saw a signal name with a square box next to it this to work
in the browser, that indicated that they were autocoalesced.) Anyway,
related signals need to be dumped with consecutive $var..$end
directives having a common prefix: a[2], a[1], a[0]. If your
simulator doesn't do this, it could be done externally by sorting the
$var lines with a special alphanumeric sort routine that preserves the
numerical values so that 1 < 2 < 10 then by reinserting the lines in
question.

If nets are specified flat earth style it shouldn't matter though you
may need to set alt_hier_delimeter in your .gtkwaverc file if other
characters like '/' are used to specify a change in hierarchy.

Hi Anthony,
A key part of the problem is that the synthesis and/or layout tool
might remove signals, or whole chunks of logic if it determines that
doing so will not affect the output. (I guess this will put a limit on
what can be reconstructed with boolean equations).

- Pad.

 

[Anthony J Bybell]

Hi Anthony,
A key part of the problem is that the synthesis and/or layout tool
might remove signals, or whole chunks of logic if it determines that
doing so will not affect the output. (I guess this will put a limit on
what can be reconstructed with boolean equations).

First let's assume that synthesis didn't mess up any functional
timings (you're not using some sort of HIS) and that it's boolean
equivalent to your original RTL. Hopefully your synthesis doesn't
remove latches/dflops though yes, many combinatorial nets will
disappear once TD mapping occurs. This is still fixable.

As buses (drivers/receivers) and dflops still exist, their
cycle-to-cycle values can be used to redrive logic cones in the
reference model...I've actually done this before to reconstruct
combinatorial logic state for various reasons, for example, like when
I've been given LSSD ringdumps from the lab:

1) Save/collect only bus values and dflop (storage element) outputs
over your desired time region. Doing the full testcase is
unnecessary.
2) Use these as stimulus to redrive a full or partial version of the
RTL boolean eqv model.
3) Save results of (2) to a dumpfile.

[YMMV, but this has worked great for me because my workcenter's
methodology doesn't put roadblocks up which prevent me from doing it.]

-t