converting std_logic_vector to integer

Discussion in 'VHDL' started by vedpsingh@gmail.com, Aug 11, 2005.

  1. Guest

    Hi all,
    The code given below has perfectly compiled, but is not giving integer
    output.
    What am I doing wrong?

    Thanks
    ved


    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.ALL;

    ENTITY conv_vec_int IS

    PORT ( a : IN std_logic_vector(7 downto 0);
    b : OUT integer range 0 to 255
    );
    END conv_vec_int;

    ARCHITECTURE behav_conv_vec_int OF conv_vec_int IS

    SIGNAL ai : std_logic_vector(7 downto 0);
    SIGNAL bi : integer range 0 to 255;

    BEGIN

    ai <= a;

    -- convert a from std_logic_vector to integer

    bi <= bi* (conv_integer(ai));

    END behav_conv_vec_int;
     
    , Aug 11, 2005
    #1
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  2. Take a look through the FAQ, there are a few things wrong with your code.
    Not to mention that this should be a function, not a component, and whether
    a function is really needed in such a simple case as this.

    I'm not going to give too much in the way of help... More fun to figure it
    out IMHO.
    http://www.vhdl.org/comp.lang.vhdl/
    is the URL to get you started.
    Ben




    <> wrote in message
    news:...
    > Hi all,
    > The code given below has perfectly compiled, but is not giving integer
    > output.
    > What am I doing wrong?
    >
    > Thanks
    > ved
    >
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.ALL;
    > USE ieee.std_logic_arith.ALL;
    > USE ieee.std_logic_unsigned.ALL;
    >
    > ENTITY conv_vec_int IS
    >
    > PORT ( a : IN std_logic_vector(7 downto 0);
    > b : OUT integer range 0 to 255
    > );
    > END conv_vec_int;
    >
    > ARCHITECTURE behav_conv_vec_int OF conv_vec_int IS
    >
    > SIGNAL ai : std_logic_vector(7 downto 0);
    > SIGNAL bi : integer range 0 to 255;
    >
    > BEGIN
    >
    > ai <= a;
    >
    > -- convert a from std_logic_vector to integer
    >
    > bi <= bi* (conv_integer(ai));
    >
    > END behav_conv_vec_int;
    >
     
    Benjamin Todd, Aug 11, 2005
    #2
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  3. Neo Guest

    Your variable bi is not assigned, so it will always have the initial
    value zero making your output also zero. the variables ai and bi are
    actually unnecessary. by the way, what is the need for a module when
    you can simply use the conversion function directly.
     
    Neo, Aug 11, 2005
    #3
  4. Guest

    by the way, what is the need for a module when
    > you can simply use the conversion function directly.


    I hope these funtions are synthesizable ??
     
    , Aug 11, 2005
    #4
  5. In this case std_logic_vector vs integer is not a question of whether it can
    be synthesised. Fundamentally hardware has no notion of integer, everything
    is wires and logic, '1' and '0'.
    i.e. using integer instead of std_logic_vector simply allows the code to be
    easier to read and more readily interpreted (in various cases) by the
    synthesis tool.


    <> wrote in message
    news:...
    >
    > by the way, what is the need for a module when
    >> you can simply use the conversion function directly.

    >
    > I hope these funtions are synthesizable ??
    >
     
    Benjamin Todd, Aug 11, 2005
    #5
  6. Guest


    > I hope these funtions are synthesizable ??

    Conversion functions are programming utilities and don't consume any
    hardware on chip. You can write a few simple programs to check this.

    KVM.
     
    , Aug 16, 2005
    #6
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