Default values on undriven ports in configuration?

Discussion in 'VHDL' started by kenm, Mar 2, 2006.

  1. kenm

    kenm Guest

    Hi,

    I have a signal which has a default value, but is undriven following a
    configuration.
    One simulator I am using gives the signal the default value. The
    testbench I have relies on this.
    A different simulator gives the signal a value of U. This causes my
    testbench to fail.
    Both are "mainstream" simulators.
    I have looked in the LRM, and it is not obvious to me which behaviour
    is correct.
    I would be very grateful as for any advice on this.

    (If replying by email, please get rid of the m after ken otherwise it
    will be treated as spam)

    Many Thanks,

    Ken Morrow

    A test case which shows the problem:-

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity PARTIAL_DRIVER is
    port (
    FRED : out std_logic_vector(7 downto 0));
    end PARTIAL_DRIVER;

    architecture TEST of PARTIAL_DRIVER is
    begin -- TEST
    FRED <= "01010101";
    end TEST;



    entity DEFAULT_VALUE is
    end DEFAULT_VALUE;


    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    architecture TEST1 of DEFAULT_VALUE is
    signal FRED : std_logic_vector(7 downto 0);

    --DEFAULT_SIGNAL is given a default value:-
    signal DEFAULT_SIGNAL : std_logic_vector(7 downto 0) := (others=>'1');
    --One simulator retains this default value.
    --The other assigns a value of 'U'.

    component DRIVER
    port (
    FRED : out std_logic_vector(7 downto 0);
    DEFAULT_SIGNAL : out std_logic_vector(7 downto 0));
    end component;

    begin -- TEST

    UUT : DRIVER
    port map (
    FRED => FRED,
    DEFAULT_SIGNAL => DEFAULT_SIGNAL);

    end TEST1;

    configuration CFG of WORK.DEFAULT_VALUE is
    for TEST1
    for UUT : DRIVER
    use entity work.PARTIAL_DRIVER
    port map (
    FRED => FRED); --NOTE DEFAULT_VALUE is
    undriven
    end for;
    end for;
    end CFG;
     
    kenm, Mar 2, 2006
    #1
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