Define type based on function return in package?

[Pentode]

I am trying to figure out a way to dynamically create a TYPE so that I can build various different loads by just changing a few constants in a library file.

Here is what Ideally I would like to achieve:

PACKAGE MyPackage IS

TYPE BUILD_LOAD_TYPE IS (
variation1,
variation2,
variation3,
variation4
);

CONSTANT BUILD_LOAD : BUILD_LOAD_TYPE := variation2;

CONSTANT VARIATION1_START_PARAMETER : INTEGER := 1
CONSTANT VARIATION1_END_PARAMETER : INTEGER := 8

CONSTANT VARIATION2_START_PARAMETER : INTEGER := 3
CONSTANT VARIATION2_END_PARAMETER : INTEGER := 12

CONSTANT VARIATION3_START_PARAMETER : INTEGER := 2
CONSTANT VARIATION3_END_PARAMETER : INTEGER := 4

CONSTANT VARIATION4_START_PARAMETER : INTEGER := 13
CONSTANT VARIATION4_END_PARAMETER : INTEGER := 26

FUNCTION start_index RETURNS INTEGER;
FUNCTION end_index RETURNS INTEGER;

-- ***NOTE1***
TYPE MYTYPE is STD_LOGIC_VECTOR(end_index DOWNTO start_index);

END MYPACKAGE

PACKAGE BODY MYPACKAGE IS
FUNCTION start_index RETURNS INTEGER IS
VARIABLE return_var :INTEGER := 0;
BEGIN
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_START_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END start_index;


FUNCTION end_index RETURNS INTEGER;
IF BUILD_LOAD = VARIATION1 THEN
return_var := VARIATION1_END_PARAMETER;
ELSE IF
...
...
...
RETURN return_var;
END end_index;
END MYPACKAGE;

--------------------------------------------------------------------------------------------
***********************************************************************
-------------------------------------------------------------------------------------------

NOTE 1:
I know that it is illegal to do this, but it illustrates what I am trying to do.

I'm pretty new to VHDL and am not very sure of the constructs available to me to achieve this kind of dynamicism.

Any and all feedback appreciated

 

[scottcarl]

Pentode,

I have run into this issue before and offer my hopeful advice. You cannot dynamically change std_logic_vector lengths within synthesizable code. Meaning the start & end value must be constants. If you think of each bit as an internal wire then you'll see that adding or subtracting wires in real time is not physically possible. Even though it may be a fixed length after the Function is called it cannot be dynamically changed in any way.

From you package naming (build_load) it appears that you want to test multiple builds of the same piece of code. If this is the case then you can use something called a "configuration statement." Bascially what you have to do is create multiple "architectures" of your same piece of code with the different std_logic_vector lenghts used in each variation. So you would have 4 different architectures and each one would have a different constant for the start & end. Then you must build the "configuration statements" (see a VHDL manual for this since. I could show you if this is this how you want to proceed.) You can then select a different 'configuration' to run a simulation or a synthesis against.

You may also want to consider using generic statements to dynamically change some values during a simulation. If you declare start & stop in a generic map. Then when running say Modelsim you can invoke the sim from the command line "vsim my_code_testbench -gstart 3 -gstop 6" where the -g proceeds the input of your 'start' and 'stop' generics called out in your top-level testbench entity.

Hope this helps,
Scott

 

[Pentode]

Thanks for the reply Scott.
I guess I used the word dynamic fairly loosely. The START and END values will not be changing dynamically when the code is running, it just sets up the TYPES and CONSTANTS at compile time, so there are no real "entities", so I'm not quite sure how the configuration statement would work.
Currently we have four products that are very similar, but have four different versions of basically the same code. I'm trying to put those four different versions into one, then just compile four times creating four different target loads so that we only have to maintain one source code set.
Therefore, before compiling, all you have to do is change the value of BUILD_LOAD and it will give you a different output, so the "wires" for any given load are fixed.
I am interested in knowing more about your proposed solution though.

Thanks again
Craig