Delay register - howto?

Discussion in 'VHDL' started by RobertBon, Nov 3, 2006.

  1. RobertBon

    RobertBon

    Joined:
    Oct 30, 2006
    Messages:
    4
    Hi all,

    I need to make a delay but i dont know how i should realise this.

    "A" ................... "B"......................."C"
    .._____ .............. _____ ............... _____
    |.........|.signal A.|........|.signal B.|.........|
    |.........|-------->|........|-------->|.........|
    |_____|.............|_____|.............|_____|
    ....|_____________________________^
    .........................signal C

    Signal B arrives 12 clock cycles later than signal C.
    When signal B arrives at "C" the signal C has allready changed but i need
    the first value.
    I would like to make a shift register to delay it.

    Can some1 please help me to realize this in a process ?

    Thanks in advance!
     
    Last edited: Nov 6, 2006
    RobertBon, Nov 3, 2006
    #1
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  2. RobertBon

    RobertBon

    Joined:
    Oct 30, 2006
    Messages:
    4
    Why is there nobody who wants to help me?
     
    RobertBon, Nov 6, 2006
    #2
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