Detecting TTL

[driftingVHDL]

Hi fellow users,

Am new to VHDL and am tasked to design a ciruitry to detect TTL levels. Appreciate some pointers on what and where to get started.

Basically, what is needed is to verify if input is logic 1 or 0 and to hold on that value output level for 25usec.

Thank You for your kind advise.

 

[driftingVHDL]

Hi fellow users,

Am new to VHDL and am tasked to design a ciruitry to detect TTL levels. Appreciate some pointers on what and where to get started.

Basically, what is needed is to verify if input is logic 1 or 0 and to hold on that value output level for 25usec.

Thank You for your kind advise.

Anyone can help point me to the right direction?

 

[driftingVHDL]

Anyone can help point me to the right direction?

 

[driftingVHDL]

Hi all,

Appreciate some help to at least point me to the right place to source for infomation. Thank!

 

[quantum_dot]

detecting TTL !

If you are trying to find out whether the input signal is TTL or CMOS or LVTTL etc, then its not possible to do the same in FPGA. You can only define IO standards for a given type of input signal.

What I could understand is that you are trying to detect a 0 to 1 transition in an input signal. Thats should not be a problem.

you can try out something similar to this

signal Din : std_logic;
signal Din_1 : std_logic;
signal Dout : std_logic;

process( clk )

if rising_edge( clk ) then
Din_1 <= Din;
end if;
Dout <= Din and ( not Din_1 ) ;

end process;


Hope you got your answer

:driver:

 

[driftingVHDL]

If you are trying to find out whether the input signal is TTL or CMOS or LVTTL etc, then its not possible to do the same in FPGA. You can only define IO standards for a given type of input signal.

What I could understand is that you are trying to detect a 0 to 1 transition in an input signal. Thats should not be a problem.

you can try out something similar to this

signal Din : std_logic;
signal Din_1 : std_logic;
signal Dout : std_logic;

process( clk )

if rising_edge( clk ) then
Din_1 <= Din;
end if;
Dout <= Din and ( not Din_1 ) ;

end process;


Hope you got your answer

:driver:

Hi quantum_dot,

Thanks for the help. This is somewhere along the line of what is intended but I guess I didn't state the requirement clearly. My humble apologies.

The input is actually an AC signal which has been converted to TTL via an external voltage divider circuitry. Basically, as long as the AC available, I would like to hold on to the output value of logic '1'. There is also an uncertainly of the input have glitches of less than 2.5ms and I would like to ignore these glitches.

Thank You!

 

[quantum_dot]

Well you need some sort of debouncing logic here. Your requirement is to neglect an high level TTL input of "less than or equal to " 2.5 ms. Define a signal (for eg AC_high ) to detect the input AC level. A simple solution can be - you detect the 0 to 1 transition as I mentioned in my last reply, then initiate a counter and run it for 2.5 ms. If the TTL input falls back to 0 ( you need to detect 1 to 0 transition here ) in this 2.5 ms duration then assert AC_high to '0' and reset the counter. Wait for another 0 to 1 transition in the input signal. Otherwise if the input signal remains high for 2.5 ms then assert the AC_high signal to '1'.

To run a counter for 2.5 ms, you need to know the clock frequency and then you can calculate the count values corresponding to 2.5 ms.

I hope this will solve your prupose.

:driver:

 

[driftingVHDL]

Well you need some sort of debouncing logic here. Your requirement is to neglect an high level TTL input of "less than or equal to " 2.5 ms. Define a signal (for eg AC_high ) to detect the input AC level. A simple solution can be - you detect the 0 to 1 transition as I mentioned in my last reply, then initiate a counter and run it for 2.5 ms. If the TTL input falls back to 0 ( you need to detect 1 to 0 transition here ) in this 2.5 ms duration then assert AC_high to '0' and reset the counter. Wait for another 0 to 1 transition in the input signal. Otherwise if the input signal remains high for 2.5 ms then assert the AC_high signal to '1'.

To run a counter for 2.5 ms, you need to know the clock frequency and then you can calculate the count values corresponding to 2.5 ms.

I hope this will solve your prupose.

:driver:

Still rather lost as not firmware guy. Do you happen to have sample code to describe it further?