diference between signal and variable?

Discussion in 'VHDL' started by jonathan castro, May 20, 2008.

  1. jonathan castro

    jonathan castro

    Joined:
    May 9, 2008
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    good morning

    can someone explain me the diference between use a signal and a variable?

    is there a pysic diference between them both?
     
    jonathan castro, May 20, 2008
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  2. jonathan castro

    jeppe

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    Find and download Evita VHDL interactive book - In chapter 6 will you find examples which explains the difference.

    A variable will get its value immediate with :=
    A signal will wait until the code ended <=
     
    jeppe, May 20, 2008
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