Digital Speedometer Design

Discussion in 'VHDL' started by johnnyjohn2009, Dec 3, 2009.

  1. johnnyjohn2009

    johnnyjohn2009

    Joined:
    Dec 3, 2009
    Messages:
    8
    Hello,

    I must first let you know that this is my final year project at University.

    I have currently been doing research into how this could be acheived using VHDL. I plan to simulate the design in software only and perhaps implement it using an FPGA if I have time.

    So far I have identified I need a pulse counter circuit counting an input pulse stream lets say every 1 second for simplicity. Taking this pulse count I plan to output the value onto a display after modifying the pulse count for calibration purposes. It all seems a bit too straight forward at the moment which is making me think I'm missing something drastic.

    If anyone has any comments to point me in the right direction to aid research, that would be great. Also if anyone can suggest a book or resource they have found useful for learning VHDL I would be most grateful.

    John
     
    johnnyjohn2009, Dec 3, 2009
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  2. johnnyjohn2009

    jeppe

    Joined:
    Mar 10, 2008
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    Denmark
    An alternative solution could be to messure the time between two pulses - it all depend on the number of pulses/second.
    Jeppe.

    Find inspiration in this: velocityreviews.com/forums/t700155-count-until-read-next-signal.html (copy the link to the Browser)
     
    Last edited: Dec 3, 2009
    jeppe, Dec 3, 2009
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