Hi everybody, i've made a division algorithm using the restoration algorithm for division. I has 0 errors, but it doesn't seem to work as it should. In the simulation it doesn't start with the "inicialization" values I gave to it (red color), is correct to do this? Thank you very much for your time
The other question is about the rotation on the same vector (green)
sROTADO(8 downto 0)<=(sROTADO(7 downto 0) & sROTADO(8));
Is there any problem with this "overwriting" on the same signal?, thank you a lot and sorry for my english! Im from Argentina!
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;
entity DIVISION is
port( clk:in std_logic;
DIVIDENDO:in std_logic_vector (3 downto 0);
DIVISOR:in std_logic_vector (3 downto 0); COCIENTE
ut std_logic_vector (3 downto 0);
RESTOut std_logic_vector (3 downto 0));
end DIVISION;
architecture FUNC of DIVISION is
signal sCONTADOR: integer;
signal sROTADO:std_logic_vector (8 downto 0);
signal sRESTA:std_logic_vector (4 downto 0);
begin
ROTARYRESTARrocess(clk)
begin
if (clk'event and clk='1') then
sROTADO<= ("00000" & DIVIDENDO);
sCONTADOR<=0;
if sCONTADOR<=4 then
sROTADO(8 downto 0)<=(sROTADO(7 downto 0) & sROTADO(8)); sRESTA(4 downto 0)<= (sROTADO(8 downto 4) - ('0' & DIVISOR));
if sRESTA(4)='1' then sROTADO(0)<='0';
sCONTADOR<=sCONTADOR+1;
elsif sRESTA(4)='0' then sROTADO(0)<='1';
sROTADO(8 downto 4)<= sRESTA(4 downto 0);
sCONTADOR<=sCONTADOR+1;
end if;
else
COCIENTE<=sROTADO(3 downto 0);
RESTO<=sROTADO(7 downto 4);
end if;
end if;
end process ROTARYRESTAR;
end FUNC;
The other question is about the rotation on the same vector (green)
sROTADO(8 downto 0)<=(sROTADO(7 downto 0) & sROTADO(8));
Is there any problem with this "overwriting" on the same signal?, thank you a lot and sorry for my english! Im from Argentina!
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_unsigned.all;
entity DIVISION is
port( clk:in std_logic;
DIVIDENDO:in std_logic_vector (3 downto 0);
DIVISOR:in std_logic_vector (3 downto 0); COCIENTE
ut std_logic_vector (3 downto 0); RESTO
ut std_logic_vector (3 downto 0)); end DIVISION;
architecture FUNC of DIVISION is
signal sCONTADOR: integer;
signal sROTADO:std_logic_vector (8 downto 0);
signal sRESTA:std_logic_vector (4 downto 0);
begin
ROTARYRESTAR
rocess(clk)begin
if (clk'event and clk='1') then
sROTADO<= ("00000" & DIVIDENDO);
sCONTADOR<=0;
if sCONTADOR<=4 then
sROTADO(8 downto 0)<=(sROTADO(7 downto 0) & sROTADO(8)); sRESTA(4 downto 0)<= (sROTADO(8 downto 4) - ('0' & DIVISOR));
if sRESTA(4)='1' then sROTADO(0)<='0';
sCONTADOR<=sCONTADOR+1;
elsif sRESTA(4)='0' then sROTADO(0)<='1';
sROTADO(8 downto 4)<= sRESTA(4 downto 0);
sCONTADOR<=sCONTADOR+1;
end if;
else
COCIENTE<=sROTADO(3 downto 0);
RESTO<=sROTADO(7 downto 4);
end if;
end if;
end process ROTARYRESTAR;
end FUNC;