dynamically accessed subrange of a vector

Discussion in 'VHDL' started by seanovsky, Nov 18, 2009.

  1. seanovsky

    seanovsky

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    Hi all,

    I have a std_logic_vector, 'D' thats 88 bits wide. I want to be able to select any 18 contiguous bits, 'B', from this vector using a signal 'S'. For example, when S = 0, select B <= D(17 downto 0), when S = 1, select B <= D(18 downto 1),..., when S = 70, select B <= D(87 downto 70).

    Instead of writing out these 71 lines, is there a way I can do something like this:

    B <= D(S+17 downto S) in order to dynamically access a subrange of a vector?

    Thanks,

    Sean
     
    seanovsky, Nov 18, 2009
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