Hi,
I have a small question. In my VHDL code i have a 32 bit std_logic_vector.
ex: data_in: in std_logic_vector (31 downto 0);
suppose in my test bench i need to assign some value to it. i need to type for all 32 bits.
ex: data_in <= "00000000000000000000000000000000"
i was wondering if there is other easier method, with which i can assign say first 5 bits differently and assign all the others bits by '0' or '1'.
thanks in advance
Milind
I have a small question. In my VHDL code i have a 32 bit std_logic_vector.
ex: data_in: in std_logic_vector (31 downto 0);
suppose in my test bench i need to assign some value to it. i need to type for all 32 bits.
ex: data_in <= "00000000000000000000000000000000"
i was wondering if there is other easier method, with which i can assign say first 5 bits differently and assign all the others bits by '0' or '1'.
thanks in advance
Milind