easier assignment of the vector in testbench

Discussion in 'VHDL' started by milindas, Jan 11, 2010.

  1. milindas

    milindas

    Joined:
    Jan 11, 2010
    Messages:
    1
    Hi,
    I have a small question. In my VHDL code i have a 32 bit std_logic_vector.
    ex: data_in: in std_logic_vector (31 downto 0);

    suppose in my test bench i need to assign some value to it. i need to type for all 32 bits.


    ex: data_in <= "00000000000000000000000000000000"

    i was wondering if there is other easier method, with which i can assign say first 5 bits differently and assign all the others bits by '0' or '1'.

    thanks in advance :)

    Milind
    milindas, Jan 11, 2010
    #1
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  2. milindas

    jerryo

    Joined:
    Jan 15, 2010
    Messages:
    1
    Hi,
    A statement like this is an option
    data <= (0 => '1', 1 => '1', 2 => '1', 4 => '1', 8 => '1', others => '0');
    You can assign specific bits in a vector and set the others to a default.

    With a 32b val, you might want to assign this way:
    data <= X"0000_0000";
    which is clean and compact, using the hex designator (X).

    regards, Jerry
    jerryo, Jan 16, 2010
    #2
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