Error in variable assignment

Discussion in 'VHDL' started by veenamgp, Sep 20, 2006.

  1. veenamgp

    veenamgp

    Joined:
    Sep 8, 2006
    Messages:
    1
    Hi,

    I want to assign a value to variable and then use this value for assigning for a signal. Such as

    c<= (a and b) or (d:= a and b);

    but its giving me an error

    near ":=": expecting: ')'
    near ")": expecting: ';'

    can anyone suggest me the solution.

    Thank you.
     
    veenamgp, Sep 20, 2006
    #1
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