Finding the execution time

Discussion in 'VHDL' started by a_Conan, Sep 2, 2005.

  1. a_Conan

    a_Conan Guest

    Hi, Suppose I have written algorithm in VHDL. This algorithm has
    sequential statements before the final result appeared.
    My question: can I calculate the time need on microsecond from the
    first input until the last output? Like in Matlab we use "tic" in first
    line and "toc" in the last line? i.e. how can I find the execution time
    for my algorithm?
    Thank you.
     
    a_Conan, Sep 2, 2005
    #1
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  2. a_Conan wrote:
    > Hi, Suppose I have written algorithm in VHDL. This algorithm has
    > sequential statements before the final result appeared.
    > My question: can I calculate the time need on microsecond from the
    > first input until the last output? Like in Matlab we use "tic" in first
    > line and "toc" in the last line? i.e. how can I find the execution time
    > for my algorithm?


    This depends on your clock frequency but from your question I think
    that your algorithm is purely combinational (combinatorial?). Thus the
    'execution' time will depend on your hardware implementation (ASIC?
    FPGA?)
    Post your code and we might help you further.

    Nicolas
     
    Nicolas Matringe, Sep 2, 2005
    #2
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  3. a_Conan

    a_Conan Guest

    Hi Nicolas, yes my algorithm depends to multiple calculations separated
    in functions and procedures such as:
    ..
    ..
    ..
    for i in 1 to M loop--start from the second row
    for k in 0 to (N - i) loop
    Matrix_out(i, k) := Matrix_in(i, i + k);
    end loop;
    for k in 0 to (i - 1) loop
    Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
    end loop;
    end loop;
    ..
    ..
    ..

    every function can call others as need.
    suppose my clock frequency is 50MHz. so how can I find the exe-time.
    I will use FPGA.
     
    a_Conan, Sep 2, 2005
    #3
  4. This is quite a big arithmetic block...
    Functions and procedure are to be used with great care in synthesizable
    code (especially procedures).
    If you don't have any synchronous process, your max speed will depend
    on the FPGA (brand & family) but anyway it may well be very slow.
    Again, post your code and we may be able to help you further.
    Remember that VHDL is definitely *not* a programming language. Always
    think hardware.

    Nicolas
     
    Nicolas Matringe, Sep 2, 2005
    #4
  5. a_Conan

    a_Conan Guest

    Do you think I can do it like this:
    ..
    ..
    T1 := NOW
    function1 :=( N1 , N2)
    function2 :=( N1 , N2)
    function3 :=( N1 , N2)
    T2 := NOW - T1;
    ..
    ..
     
    a_Conan, Sep 2, 2005
    #5
  6. a_Conan

    Guest

    Stop thinking software !!!

    Your two loops with 2 dimensions vector cannot be synthesizable !!

    I think you better use a RAM and make transfert inside the RAM...

    Are you just doing simulation or you want to implant it in a FPGA
     
    , Sep 2, 2005
    #6
  7. a_Conan

    Guest

    Stop thinking software !!!

    Your two loops with 2 dimensions vector cannot be synthesizable !!

    I think you better use a RAM and make transfert inside the RAM...

    Are you just doing simulation or you want to implant it in a FPGA
     
    , Sep 2, 2005
    #7
  8. a_Conan

    a_Conan Guest

    Sorry patrick, do you mean I cannot synthesize the upper code on my
    FPGA?
    Are you sure?
     
    a_Conan, Sep 2, 2005
    #8
  9. a_Conan

    a_Conan Guest

    Ok, Patric can you tell me how can I do
    for i in 1 to M loop--start from the second row
    for k in 0 to (N - i) loop
    Matrix_out(i, k) := Matrix_in(i, i + k);
    end loop;
    for k in 0 to (i - 1) loop
    Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
    end loop;
    end loop;

    in RAM to make it synthesizable ?

    Thanks
     
    a_Conan, Sep 3, 2005
    #9
  10. a_Conan wrote:

    > Ok, Patric can you tell me how can I do
    > for i in 1 to M loop--start from the second row
    > for k in 0 to (N - i) loop
    > Matrix_out(i, k) := Matrix_in(i, i + k);
    > end loop;
    > for k in 0 to (i - 1) loop
    > Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
    > end loop;
    > end loop;
    >
    > in RAM to make it synthesizable ?


    1st of all: Get knowledge about flipflops, combinational logic and
    latches. Make yourself familiar with the concept of a state machine -
    especially a synthesizable state machine in VHDL.

    2nd: Think about a data path, on which such an algorithm may be
    implemented. You need a state machine and inside some states you connect
    some blocks (registers, arithmetic units...) together. Everything
    step-by-step, controlled by a state machine.


    VHDL may be used like a programming language, but only for simulation
    purpose. If you want to model real hardware you have to think hardware.

    Ralf
     
    Ralf Hildebrandt, Sep 3, 2005
    #10
  11. a_Conan

    a_Conan Guest

    Ok Ralf , I tried to use a type like:

    type Matrix is array (0 to M, 0 to N) of unsigned (7 downto 0);

    I have background about combinational logic, because I am a
    computereEngineer. but I have started with VHDL before 3 weeks ago.
    please give the correct way to define
    type Matrix is array (0 to M, 0 to N) of unsigned (7 downto 0);
    in VHDL

    Best regards,
     
    a_Conan, Sep 4, 2005
    #11
  12. a_Conan

    Guest

    a_Conan wrote:
    > Ok, Patric can you tell me how can I do
    > for i in 1 to M loop--start from the second row
    > for k in 0 to (N - i) loop
    > Matrix_out(i, k) := Matrix_in(i, i + k);
    > end loop;
    > for k in 0 to (i - 1) loop
    > Matrix_out(i, N - k) := Matrix_in(i, i - k - 1);
    > end loop;
    > end loop;


    You should, as everyone has replied, try to model this code for
    hardware. Here are some pointers on how you can model the above code
    for hardware.
    As I understand perhaps your output matrix is a shofted version of your
    input matrix.
    (1) So, first create a RAM to store your input matrix .
    (2) Then, make two counters (You have two cases for k!), the output of
    which you should connect to the address of the RAM.
    (3) Before this, a multiplexer should check the vaues of k and select
    one of the two addresses depending on the value of k.
    (4) The output of RAM may be stored (if required) in another RAM.

    ----------This is just a very crass model of your code. Some refinement
    can lead to exact solution.
     
    , Sep 4, 2005
    #12
  13. a_Conan wrote:

    > Ok Ralf , I tried to use a type like:
    >
    > type Matrix is array (0 to M, 0 to N) of unsigned (7 downto 0);


    Uhmmm ... well ... just a definition a 3D array. This alone does not
    make hardware. It is the same as "my car has 4 wheels" - nothing more.

    What you need is something, that says: "get one element out of the
    array, move it to register X, do something with it and store it in
    register Y" - just like "open the car-door, get in, plug the key..."

    Remember, that multi-dimensional arrays may not be supported by your
    synthesis tool - but you may break this down later.


    > I have background about combinational logic, because I am a
    > computereEngineer.


    As a computer engineer you should be familiar with the idea of
    sequential logic, too. O.k. - a lot of software programs are
    sequentially, because instructions are executed step-by-step, but the
    idea of a state machine exists in software engineering, too!

    For hardware description sequential logic and especially state machines
    are nessecary, because with only comb. logic you can't do a lot.


    > but I have started with VHDL before 3 weeks ago.


    Did you read a book about HDL modelling during this time? I do not talk
    about a book, that tells you the synthax of VHDL or the BNF of it, but a
    book, that makes you familiar with flipflops, latches, counters, state
    machines and so on.
    For me "HDL chip design" from Doone Publications was very helpful.


    Ralf
     
    Ralf Hildebrandt, Sep 4, 2005
    #13
  14. a_Conan

    a_Conan Guest

    I will try my best :) Thanks for all...
     
    a_Conan, Sep 5, 2005
    #14
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