Getting up-to-date libraries for timing simulation

Discussion in 'VHDL' started by valentin tihomirov, Jan 1, 2004.

  1. I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting
    VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown
    identifier "X_ROC"* error. X_ROC is the only primitive that cannot be found
    in the SIMPRIM library provided with ActiveHDL. What is the standard
    procedure of getting up-to-date libraries: asking library sources from
    Xilinx or precompiled .lib file from Aldec? Simulator vendors somehow
    optimize pre-compiled libraries.
     
    valentin tihomirov, Jan 1, 2004
    #1
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  2. valentin tihomirov wrote:
    > I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting
    > VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown
    > identifier "X_ROC"* error.


    Consider writing your own vhdl code and
    siming it before synthesis.

    -- Mike Treseler
     
    Mike Treseler, Jan 5, 2004
    #2
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  3. > Consider writing your own vhdl code and
    > siming it before synthesis.

    Excuse me, what does this mean? BTW, I have resolved the problem by
    downloading last version (6.2) of SW from Aldec.
     
    valentin tihomirov, Jan 5, 2004
    #3
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