Help with procedure

Discussion in 'VHDL' started by Willem Oosthuizen, Aug 20, 2003.

  1. I use the following code in a process, and it works as intended.

    if pci_trdyn /= '0' then
    while pci_trdyn /= '0' loop
    wait for clock_period;
    end loop;
    wait for clock_period;
    else
    wait for clock_period;
    end if;

    I would like to replace this code with

    WaitSig(pci_trdyn ,'0',Clock_Period);

    where WaitSig is defined as

    procedure WaitSig(Sig,State : in std_logic; Clock_Period : in time) is
    begin
    if Sig /= State then
    while Sig /= State loop
    wait for clock_period;
    end loop;
    wait for clock_period;
    else
    wait for clock_period;
    end if;
    end procedure;

    This does not work. Why? Is it because signals are not updated dynamically
    while a procedure executes?
    Is there another mechanism I can use to simplify my code?
    Willem Oosthuizen, Aug 20, 2003
    #1
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  2. I think the problem is the procedure

    > procedure WaitSig(Sig,State : in std_logic; Clock_Period : in time) is


    This is equal to:
    procedure WaitSig( CONSTANT Sig,State : in std_logic; CONSTANT Clock_Period
    : in time) is

    and you don't want the constant value ("call by value") but since the value
    of the signals
    are changed when time progress you want probably the actual value ("call by
    reference").
    Make this explicit as follows:
    procedure WaitSig(SIGNAL Sig,State : in std_logic; Clock_Period : in time)
    is
    (assuming that Clock_period is a constant value, otherwise add SIGNAL to for
    'Clock_period')

    Egbert Molenkamp

    "Willem Oosthuizen" <> wrote in message
    news:bhv98c$mcj$...
    > I use the following code in a process, and it works as intended.
    >
    > if pci_trdyn /= '0' then
    > while pci_trdyn /= '0' loop
    > wait for clock_period;
    > end loop;
    > wait for clock_period;
    > else
    > wait for clock_period;
    > end if;
    >
    > I would like to replace this code with
    >
    > WaitSig(pci_trdyn ,'0',Clock_Period);
    >
    > where WaitSig is defined as
    >
    > procedure WaitSig(Sig,State : in std_logic; Clock_Period : in time) is
    > begin
    > if Sig /= State then
    > while Sig /= State loop
    > wait for clock_period;
    > end loop;
    > wait for clock_period;
    > else
    > wait for clock_period;
    > end if;
    > end procedure;
    >
    > This does not work. Why? Is it because signals are not updated dynamically
    > while a procedure executes?
    > Is there another mechanism I can use to simplify my code?
    >
    >
    Egbert Molenkamp, Aug 20, 2003
    #2
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