homework: flipflips with async reset

Discussion in 'VHDL' started by Bryan Johnson, Jul 6, 2006.

  1. Hi,
    the following task is from a homework:

    Write a synthesis-compliant process that creates 10
    clock-edge-controlled flipflops using asynchonous reset.

    Now my question:
    How can a process create something?

    TIA
    Bryan
    Bryan Johnson, Jul 6, 2006
    #1
    1. Advertising

  2. Bryan Johnson

    Zara Guest

    On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <> wrote:

    >Hi,
    >the following task is from a homework:
    >
    >Write a synthesis-compliant process that creates 10
    >clock-edge-controlled flipflops using asynchonous reset.
    >
    >Now my question:
    >How can a process create something?
    >



    Within an entity, a process can create almost anything.

    For instance:

    process(some_signal,clock)
    begin
    if some_signal='0' then
    output<'0';
    elsif rising_edge(clock) then
    output<='1';
    end if;
    end process;


    Completing this process with all necessary headers, you will have a
    process that "creates" a single flip_flop with asynchronous active-low
    reset, and fed back so that it will toggle on every clock edge.

    Once you understand it , you will be perfectly able to do your
    homework.

    Zara
    Zara, Jul 6, 2006
    #2
    1. Advertising

  3. You have to go back to basics, if you don't understand that then you've
    missed the VHDL 101...

    VHDL is a _Hardware Description Language_

    The synthesis tool generates circuits equivalent to the processes that you
    write.

    ......Google, Wikipedia.... =)

    HTH
    Ben

    "Bryan Johnson" <> wrote in message
    news:Eq7rg.23169$...
    > Hi,
    > the following task is from a homework:
    >
    > Write a synthesis-compliant process that creates 10 clock-edge-controlled
    > flipflops using asynchonous reset.
    >
    > Now my question:
    > How can a process create something?
    >
    > TIA
    > Bryan
    Benjamin Todd, Jul 6, 2006
    #3
  4. On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <> wrote:


    >the following task is from a homework:
    >
    >Write a synthesis-compliant process that creates 10
    >clock-edge-controlled flipflops using asynchonous reset.
    >
    >Now my question:
    >How can a process create something?


    Tee hee. Great Mysteries of the Universe, #37: How
    can a homework problem do anything useful?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jul 6, 2006
    #4
  5. On 06.07.2006 14:54, * Zara wrote:
    > On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <> wrote:
    >
    >> Hi,
    >> the following task is from a homework:
    >>
    >> Write a synthesis-compliant process that creates 10
    >> clock-edge-controlled flipflops using asynchonous reset.
    >>
    >> Now my question:
    >> How can a process create something?
    >>

    >
    >
    > Within an entity, a process can create almost anything.
    >
    > For instance:
    >
    > process(some_signal,clock)
    > begin
    > if some_signal='0' then
    > output<'0';
    > elsif rising_edge(clock) then
    > output<='1';
    > end if;
    > end process;
    >
    >
    > Completing this process with all necessary headers, you will have a
    > process that "creates" a single flip_flop with asynchronous active-low
    > reset, and fed back so that it will toggle on every clock edge.
    >
    > Once you understand it , you will be perfectly able to do your
    > homework.
    >
    > Zara


    Thank you for your answer.
    Here is what i got so far:

    entity flipflop is
    port (
    reset, clock, d_in : in std_logic;
    d_out : out std_logic);
    end entity;

    architecture behavior of flipflop is
    begin
    process (clock, reset)
    begin
    if (reset = '1') then
    d_out <= '0';
    elsif (rising_edge(clock)) then
    d_out <= d_in;
    end if;
    end process;
    end architecture;

    This is one flipflop with asynchronous reset.
    How to write a process that creates 10 of those?
    Does create mean "generate"?

    Bryan
    Bryan Johnson, Jul 6, 2006
    #5
  6. Maybe this is a solution:

    entity flipflop10 is
    port (
    reset, clock : in std_logic;
    d_in : in std_logic_vector(1 to 10);
    d_out : out std_logic_vector(1 to 10));
    end entity;

    architecture behavior of flipflop is
    begin
    process (clock, reset)
    begin
    if (reset = '1') then
    d_out <= (others => '0');
    elsif (rising_edge(clock)) then
    d_out <= d_in;
    end if;
    end process;
    end architecture;

    Or am I missing something here?

    Bryan
    Bryan Johnson, Jul 6, 2006
    #6
  7. Bryan Johnson wrote:

    > Maybe this is a solution:

    ....

    Yes, this is the standard solution.


    > entity flipflop10 is
    > port (
    > reset, clock : in std_logic;
    > d_in : in std_logic_vector(1 to 10);
    > d_out : out std_logic_vector(1 to 10));
    > end entity;


    It is not wrong, but usually vectors are defined in downward direction
    having the LSB 0 - e.g.

    d_in : in std_logic_vector(9 downto 0);

    The reason is easier conversion to other types, like integer.


    > Or am I missing something here?


    No. If you want to make the next step in learning VHDL you could have a
    look at the for-generate statement.

    gen_label : for N in 0 to 9 generate
    -- code for a single flipflop d_out(N) inside
    -- that selects d_in(N)
    end generate;


    Ralf
    Ralf Hildebrandt, Jul 6, 2006
    #7
  8. On 06.07.2006 16:56, * Ralf Hildebrandt wrote:
    >
    > No. If you want to make the next step in learning VHDL you could have a
    > look at the for-generate statement.
    >
    > gen_label : for N in 0 to 9 generate
    > -- code for a single flipflop d_out(N) inside
    > -- that selects d_in(N)
    > end generate;


    Hi Ralf,

    I know of the for-generate statement.
    But can it be used inside a process, as my
    homework question (see first post) says?
    I don't think this makes sense.

    Bryan
    Bryan Johnson, Jul 6, 2006
    #8
  9. Bryan Johnson wrote:

    >> gen_label : for N in 0 to 9 generate
    >> -- code for a single flipflop d_out(N) inside
    >> -- that selects d_in(N)
    >> end generate;


    > I know of the for-generate statement.
    > But can it be used inside a process, as my
    > homework question (see first post) says?


    In your 1st question it is not mentioned, that a for-generate or
    if-generate should be coded _inside_ a process. That is not possible -
    the generates have to be always outside.

    Ralf
    Ralf Hildebrandt, Jul 6, 2006
    #9
  10. Bryan Johnson

    Ricardo Guest

    Inside the process you may try for..loop.

    Ricardo

    Bryan Johnson escreveu:

    > On 06.07.2006 16:56, * Ralf Hildebrandt wrote:
    > >
    > > No. If you want to make the next step in learning VHDL you could have a
    > > look at the for-generate statement.
    > >
    > > gen_label : for N in 0 to 9 generate
    > > -- code for a single flipflop d_out(N) inside
    > > -- that selects d_in(N)
    > > end generate;

    >
    > Hi Ralf,
    >
    > I know of the for-generate statement.
    > But can it be used inside a process, as my
    > homework question (see first post) says?
    > I don't think this makes sense.
    >
    > Bryan
    Ricardo, Jul 7, 2006
    #10
  11. Bryan Johnson

    john Guest

    Hi Jonathan,
    If you do want to answer the question then please do not answer it but
    do not pass unnecssary remarks.
    Regards
    Thanks
    Jonathan Bromley wrote:
    > On Thu, 06 Jul 2006 12:33:41 GMT, Bryan Johnson <> wrote:
    >
    >
    > >the following task is from a homework:
    > >
    > >Write a synthesis-compliant process that creates 10
    > >clock-edge-controlled flipflops using asynchonous reset.
    > >
    > >Now my question:
    > >How can a process create something?

    >
    > Tee hee. Great Mysteries of the Universe, #37: How
    > can a homework problem do anything useful?
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
    >
    > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
    >
    > http://www.MYCOMPANY.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.
    john, Jul 7, 2006
    #11
  12. On 7 Jul 2006 11:37:52 -0700, john <> wrote:

    >If you do want to answer the question then please do not answer it but
    >do not pass unnecssary remarks.


    Humbug. The whole of Usenet is "unnecessary". The directly
    helpful replies that I and many others consistently post here
    are "unnecessary". Pray do not deny me some harmless
    "unnecessary" fun.

    In fact the OP posed an intriguing question :

    >> >How can a process create something?


    which nicely challenges the kind of sloppy wording (and,
    I fear, sloppy thinking) that characterises many homework
    and textbook problems in our field. I understood him
    to be quite reasonably poking fun at that, and answered
    in kind. It seems that I misunderstood; that happens
    from time to time.

    Anyway, the correct answer to the question: The only
    thing a VHDL process can create is transactions on
    signals, and even that only when its enclosing design
    unit is instantiated and the process executes.
    However, a synthesis tool may well read such a process
    and use it to control the inference of some hardware;
    it would then be reasonable to say that the process
    has "created" the hardware.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Jul 7, 2006
    #12
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Jason Berringer

    Async reset

    Jason Berringer, Oct 20, 2004, in forum: VHDL
    Replies:
    14
    Views:
    1,542
    Subroto Datta
    Oct 26, 2004
  2. ALuPin

    Discussion "Async Reset"

    ALuPin, Oct 25, 2004, in forum: VHDL
    Replies:
    2
    Views:
    648
    Raghavendra
    Oct 27, 2004
  3. Guest
    Replies:
    0
    Views:
    670
    Guest
    Feb 25, 2004
  4. Niv
    Replies:
    9
    Views:
    817
    Mike Treseler
    Jan 5, 2006
  5. Steven
    Replies:
    0
    Views:
    348
    Steven
    Nov 30, 2005
Loading...

Share This Page