homework: flipflips with async reset

[Bryan Johnson]

Hi,
the following task is from a homework:

Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.

Now my question:
How can a process create something?

TIA
Bryan

 

[Zara]

Hi,
the following task is from a homework:

Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.

Now my question:
How can a process create something?

Within an entity, a process can create almost anything.

For instance:

process(some_signal,clock)
begin
if some_signal='0' then
output<'0';
elsif rising_edge(clock) then
output<='1';
end if;
end process;


Completing this process with all necessary headers, you will have a
process that "creates" a single flip_flop with asynchronous active-low
reset, and fed back so that it will toggle on every clock edge.

Once you understand it , you will be perfectly able to do your
homework.

Zara

 

[Benjamin Todd]

You have to go back to basics, if you don't understand that then you've
missed the VHDL 101...

VHDL is a _Hardware Description Language_

The synthesis tool generates circuits equivalent to the processes that you
write.

......Google, Wikipedia.... =)

HTH
Ben

 

[Jonathan Bromley]

the following task is from a homework:

Write a synthesis-compliant process that creates 10
clock-edge-controlled flipflops using asynchonous reset.

Now my question:
How can a process create something?

Tee hee. Great Mysteries of the Universe, #37: How
can a homework problem do anything useful?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Bryan Johnson]

Within an entity, a process can create almost anything.

For instance:

process(some_signal,clock)
begin
if some_signal='0' then
output<'0';
elsif rising_edge(clock) then
output<='1';
end if;
end process;


Completing this process with all necessary headers, you will have a
process that "creates" a single flip_flop with asynchronous active-low
reset, and fed back so that it will toggle on every clock edge.

Once you understand it , you will be perfectly able to do your
homework.

Zara

Thank you for your answer.
Here is what i got so far:

entity flipflop is
port (
reset, clock, d_in : in std_logic;
d_out : out std_logic);
end entity;

architecture behavior of flipflop is
begin
process (clock, reset)
begin
if (reset = '1') then
d_out <= '0';
elsif (rising_edge(clock)) then
d_out <= d_in;
end if;
end process;
end architecture;

This is one flipflop with asynchronous reset.
How to write a process that creates 10 of those?
Does create mean "generate"?

Bryan

 

[Bryan Johnson]

Maybe this is a solution:

entity flipflop10 is
port (
reset, clock : in std_logic;
d_in : in std_logic_vector(1 to 10);
d_out : out std_logic_vector(1 to 10));
end entity;

architecture behavior of flipflop is
begin
process (clock, reset)
begin
if (reset = '1') then
d_out <= (others => '0');
elsif (rising_edge(clock)) then
d_out <= d_in;
end if;
end process;
end architecture;

Or am I missing something here?

Bryan

 

[Ralf Hildebrandt]

Maybe this is a solution:

....

Yes, this is the standard solution.

entity flipflop10 is
port (
reset, clock : in std_logic;
d_in : in std_logic_vector(1 to 10);
d_out : out std_logic_vector(1 to 10));
end entity;

It is not wrong, but usually vectors are defined in downward direction
having the LSB 0 - e.g.

d_in : in std_logic_vector(9 downto 0);

The reason is easier conversion to other types, like integer.

Or am I missing something here?

No. If you want to make the next step in learning VHDL you could have a
look at the for-generate statement.

gen_label : for N in 0 to 9 generate
-- code for a single flipflop d_out(N) inside
-- that selects d_in(N)
end generate;


Ralf

 

[Bryan Johnson]

No. If you want to make the next step in learning VHDL you could have a
look at the for-generate statement.

gen_label : for N in 0 to 9 generate
-- code for a single flipflop d_out(N) inside
-- that selects d_in(N)
end generate;

Hi Ralf,

I know of the for-generate statement.
But can it be used inside a process, as my
homework question (see first post) says?
I don't think this makes sense.

Bryan

 

[Ralf Hildebrandt]

I know of the for-generate statement.
But can it be used inside a process, as my
homework question (see first post) says?

In your 1st question it is not mentioned, that a for-generate or
if-generate should be coded _inside_ a process. That is not possible -
the generates have to be always outside.

Ralf

 

[Ricardo]

Inside the process you may try for..loop.

Ricardo

Bryan Johnson escreveu:

 

[john]

Hi Jonathan,
If you do want to answer the question then please do not answer it but
do not pass unnecssary remarks.
Regards
Thanks

 

[Jonathan Bromley]

If you do want to answer the question then please do not answer it but
do not pass unnecssary remarks.

Humbug. The whole of Usenet is "unnecessary". The directly
helpful replies that I and many others consistently post here
are "unnecessary". Pray do not deny me some harmless
"unnecessary" fun.

In fact the OP posed an intriguing question :

which nicely challenges the kind of sloppy wording (and,
I fear, sloppy thinking) that characterises many homework
and textbook problems in our field. I understood him
to be quite reasonably poking fun at that, and answered
in kind. It seems that I misunderstood; that happens
from time to time.

Anyway, the correct answer to the question: The only
thing a VHDL process can create is transactions on
signals, and even that only when its enclosing design
unit is instantiated and the process executes.
However, a synthesis tool may well read such a process
and use it to control the inference of some hardware;
it would then be reasonable to say that the process
has "created" the hardware.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.