How to decide the stages of a pipeline device?

Discussion in 'VHDL' started by Cuthbert, Jul 28, 2008.

  1. Cuthbert

    Cuthbert Guest

    Good day, everyone,

    Is there any basic principles for designing a pipeline device or
    does anybody know books or papers I can look into it? Thanks in
    advance.


    Cuthbert
     
    Cuthbert, Jul 28, 2008
    #1
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  2. Cuthbert wrote:

    > Is there any basic principles for designing a pipeline device or
    > does anybody know books or papers I can look into it? Thanks in
    > advance.


    It's more of a clocked design style than a device;
    a set of parallel shift registers with logic at each node.
    The trick is to line up the outputs.
    See http://en.wikipedia.org/wiki/Pipeline_(computing)
    Synthesis can do some of the work if you turn on
    register retiming.

    -- Mike Treseler
     
    Mike Treseler, Jul 28, 2008
    #2
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  3. Cuthbert

    Cuthbert Guest

    Thank you for your help. :)

    Cuthbert

    On Jul 30, 12:30 pm, glen herrmannsfeldt <>
    wrote:
    > Cuthbert wrote:
    > > Is there any basic principles for designing a pipeline device or
    > > does anybody know books or papers I can look into it? Thanks in
    > > advance.

    >
    > It depends somewhat, but there is some literature for
    > "systolic array" processors that should help.
    >
    > There are also books on pipelined computers from some
    > years ago that might also be useful.
    >
    > -- glen
     
    Cuthbert, Jul 31, 2008
    #3
  4. Cuthbert

    kit Guest

    On Jul 30, 11:41 pm, Cuthbert <> wrote:
    > Thank you for your help. :)
    >
    > Cuthbert
    >
    > On Jul 30, 12:30 pm, glen herrmannsfeldt <>
    > wrote:
    >
    > > Cuthbert wrote:
    > > >     Is there any basic principles for designing a pipeline device or
    > > > does anybody know books or papers I can look into it? Thanks in
    > > > advance.

    >
    > > It depends somewhat, but there is some literature for
    > > "systolic array" processors that should help.

    >
    > > There are also books on pipelined computers from some
    > > years ago that might also be useful.

    >
    > > -- glen

    >
    >


    Hi,

    Here is a very crude formula, mostly for academic purposes, which
    might be of some use to you in your understanding:

    Latency >= NS(C2Q) + NS(Input Setup) + (Logic Delay/NS) + 2 (Skew)

    Latency = Cycle Time or Freq of operation;
    NS => Number of stages;
    And it is obvious that I have considered the worst skew.

    All the best.

    Krishna Praveen M. R.
     
    kit, Jul 31, 2008
    #4
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