W
Weng Tianxiang
Hi,
I am in VHDL.
I have the following statements:
type integer_array is array(natural range <>) of integer;
type cs_type is array (0 to N) of integer_array (1 to Nmax);
signal cs : cs_type;
If those statements live within an architecture, everything goes well.
But if I make the signal cs as a port of the entity, the problem
arise:
I must specify integer_array and cs_type somewhere in the project
globally.
Is anything I can do to use the type declarations locally in the file
of the entity?
Thank you.
Weng
I am in VHDL.
I have the following statements:
type integer_array is array(natural range <>) of integer;
type cs_type is array (0 to N) of integer_array (1 to Nmax);
signal cs : cs_type;
If those statements live within an architecture, everything goes well.
But if I make the signal cs as a port of the entity, the problem
arise:
I must specify integer_array and cs_type somewhere in the project
globally.
Is anything I can do to use the type declarations locally in the file
of the entity?
Thank you.
Weng