how to delay the signal?

[koce]

Hi everyone,

I use Altera MAXII CPLD for my project. I program it
using Quartus II software and VHDL language. With CPLD
I control switches using one global clock signal. For
one switch, I want to turn it on not on the rising
edge of the global clock but to delay the turning on
(10ns for example).
In my VHDL code I use generic type of data.
generic (Tdelay: time:=10ns);
I use thisconstant when I want to delay my signal:
if (clock'event and clock='1')then
s1='1' after Tdelay;
VHDL syntax verification is OK but I have a problem
when I want to do final compilation.
The error is something like type time does not
match string literal[/QUOTE]
I think that it is because I use generic type of data.
If you know the other way of delaying signal using
VHDL code please share with me. You will help me a
lot!

Thanks
Bojan

 

[KJ]

Hi everyone,

I use Altera MAXII CPLD for my project. I program it
using Quartus II software and VHDL language. With CPLD
I control switches using one global clock signal. For
one switch, I want to turn it on not on the rising
edge of the global clock but to delay the turning on
(10ns for example).

Usually the reasons for wanting to delay things by some absolute time delay
relative to the clock are poor design practice.

In my VHDL code I use generic type of data.
generic (Tdelay: time:=10ns);
I use thisconstant when I want to delay my signal:
if (clock'event and clock='1')then
s1='1' after Tdelay;

You won't be implementing this in a MAXII CPLD then....or any other offering
that I'm aware of from Altera...or Xilinx...or Lattice...or Actel, etc.

VHDL syntax verification is OK but I have a problem
when I want to do final compilation.

By 'final' I'm guessing that you mean trying to synthesize the design (i.e.
running Quartus to produce a bit file to program the part).

The error is something like type time does not
match string literal

I think that it is because I use generic type of data.[/QUOTE]

I've passed generics of type time into entities and they get handled
correctly and synthesized using Quartus so that is not the problem you're
having....but my usage of the generic time is quite different than how
you're trying to use it, although I was using it to accomplish the same
function (i.e. to delay some signal, or create a signal with a specified
pulse width, etc.)

If you know the other way of delaying signal using
VHDL code please share with me. You will help me a
lot!

1. "s1='1' after Tdelay" is not synthesizable in any FPGA/CPLD on the market
today because of the "after Tdelay". You can't use it if you intend to
synthesize that code to produce a part on a board.

2. VHDL 'time' types can only be used to compute other constants.

The way to produce a delay in a synchronous design is to pass in two
generics (both of type time). The first being the delay you'd like (i.e.
Tdelay), the second being the clock period that you intend to run the design
at (calling it Clock_Period for example). Now inside the architecture you
define an integer that has a range that goes from 0 to (Tdelay /
Clock_Period).

constant Max_Delay_Count: natural := (Tdelay / Clock_Period);
signal Delay_Counter: natural range 0 to (Max_Delay_Count - 1);

Now build a counter that counts from 0 to (Max_Delay_Count - 1) and go from
there.

Having said all of that, if your intended delay really is of the order of 10
ns then this technique won't work unless you have a 100 MHz clock or faster.
In that case, you'll need an external delay line part on your board.

Kevin Jennings

 

[raullim7]

my clock period is 10ns (clock is at 100MHz) and my desired delay is
2.5ns.
in this case, my Max_Delay_Count will be 0.25 and thus, the counter
range will be 0 to -0.75??
but how is the counter going to run from 0 to -0.75? please advise.
thanks

 

[KJ]

my clock period is 10ns (clock is at 100MHz) and my desired delay is
2.5ns.
in this case, my Max_Delay_Count will be 0.25 and thus, the counter
range will be 0 to -0.75??
but how is the counter going to run from 0 to -0.75? please advise.
thanks

At the risk of being redundant, since it appears you didn't read (or
possibly understand) the first post, I'll try again.

1. Usually the reasons for wanting to delay things by some absolute
time delay
relative to the clock are poor design practice. What is your reason
for wanting the 2.5 ns delay in the first place?

2. If your intended delay is 2.5 ns then this technique (i.e. the
previously posted counter approach) won't work unless you have a 400
MHz clock or faster. If you don't have that, then you'll need an
external delay line part on your board.

3. Without such a clock, you won't be implementing this in a MAXII
CPLD then....or any other offering that I'm aware of from Altera...or
Xilinx...or Lattice...or Actel, etc.

Kevin Jennings

 

[Brian Drummond]

my clock period is 10ns (clock is at 100MHz) and my desired delay is
2.5ns.
in this case, my Max_Delay_Count will be 0.25 and thus, the counter
range will be 0 to -0.75??
but how is the counter going to run from 0 to -0.75? please advise.
thanks

Double the frequency to 200MHz and use the 180 degree (i.e. inverted) clock
output.

- Brian

 

[KJ]

Double the frequency to 200MHz and use the 180 degree (i.e. inverted) clock
output.

And then cross your fingers with the hope that the clock duty cycle,
input voltage thresholds and clock skew are adequate.

KJ

 

[Brian Drummond]

And then cross your fingers with the hope that the clock duty cycle,
input voltage thresholds and clock skew are adequate.

Oh, absolutely!

(though I'd trust the 180 degree output from a DCM at 200MHz at least as much as
the main output at 400MHz)

- Brian