How to get most significant bits

Discussion in 'VHDL' started by qharz, Jun 23, 2009.

  1. qharz

    qharz Guest

    Hi
    How to get 17 oldest bits from variable std_logic_vector (17 + 2*CONSTANT
    downto 0)
    CONSTANT is changing manually before every compilation.

    Thanks
    --
    qharz
     
    qharz, Jun 23, 2009
    #1
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  2. qharz

    JimLewis Guest


    > Hi
    > How to get 17 oldest bits from variable std_logic_vector (17 + 2*CONSTANT
    > downto 0)
    > CONSTANT is changing manually before every compilation.
    >
    > Thanks
    > --
    > qharz



    signal V : std_logic_vector (17 + 2*MY_CONST downto 0) ;
    signal L, R : std_logic_vector(16 downto 0) ;


    -- 17 left most bits:
    L <= V(V'left downto V'left - 16) ;

    -- 17 right most bits
    R <= V(16 downto 0) ;


    Not sure what you mean by oldest, so those are my best guesses.

    Cheers,
    Jim
     
    JimLewis, Jun 23, 2009
    #2
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  3. qharz

    KJ Guest

    "JimLewis" <> wrote in message
    news:1d488fdc-8e76-4ed2-b532-
    >
    > Not sure what you mean by oldest, so those are my best guesses.
    >


    The older ones tend to be on the right...

    KJ
     
    KJ, Jun 23, 2009
    #3
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