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- Oct 26, 2007
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Hi,
I grouped several LUTs in my design into an RLOC, and put them in a U_SET with the following line in the VHDL file
attribute U_SET of sliceup_i: label is "SWITCH_CHAIN";
Now I would like to position the whole group using absolute positioning on the FPGA (Virtex-II Pro). I tried to do it using the following line in the UCF file:
SET SWITCH_CHAIN RLOC_ORIGIN = "X49Y0" ;
Although this line does what I intend it to do (I can see the circuit in place using the FPGA editor), it does signal an error :
ERROR:ConstraintSystem - In file: combined.ucf(5): 'SET' is not a valid
design object type to associate constraints with.
What is the proper way of setting the RLOC_ORIGIN of a U_SET from within the UCF file?
Thanks,
Berk
I grouped several LUTs in my design into an RLOC, and put them in a U_SET with the following line in the VHDL file
attribute U_SET of sliceup_i: label is "SWITCH_CHAIN";
Now I would like to position the whole group using absolute positioning on the FPGA (Virtex-II Pro). I tried to do it using the following line in the UCF file:
SET SWITCH_CHAIN RLOC_ORIGIN = "X49Y0" ;
Although this line does what I intend it to do (I can see the circuit in place using the FPGA editor), it does signal an error :
ERROR:ConstraintSystem - In file: combined.ucf(5): 'SET' is not a valid
design object type to associate constraints with.
What is the proper way of setting the RLOC_ORIGIN of a U_SET from within the UCF file?
Thanks,
Berk