How to use the 'event in Xilinx?

[VHDLstudent]

Hello

I have some troubles in my design since i only want a thing to happend at the edge when the signal gets high, but insted it happens again and again while the signal is still high.

Then I tried the this:

if blast'event and blast = '1' then

I thought that I could use it on all signals but it seems that it only works on the clock? how can i solve it?


Regards and thanks for your help and time!

 

[jeppe]

it should be ok -inside a process like:

Process (Blast)
begin
if ....

An alternative to your line could be

if rising_edge( Blast) then ...

 

[VHDLstudent]

I've tried that, but then I get this error:

ERROR:Xst:827 - "C:/test.vhd" line 42: Signal signal_name cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

It seems like my version of Xilinx doesn't support it? I Have the Student Version of Xilinx does that might course the problem?

Thanx for your help so far.

 

[JohnDuq]

How about if you generate a pulse that is one clock wide at the rising edge of blast? Something like this in a synchronous process:

if (blast = "1") and (last_blast = "0") then
blast_edge <= "1";
else blast_edge <= "0";
last_blast <= blast; -- previous clocks data

Now you can use the state of blast_edge = "1" as your enable.

 

[VHDLstudent]

Thanx for you answer JohnDug. I guess that could work too..

But I just solved the problem by adding an extra state where I'm just setting the signal low again after one clock cyclus.

Regards