How to use the 'event in Xilinx?

Discussion in 'VHDL' started by VHDLstudent, May 4, 2009.

  1. VHDLstudent

    VHDLstudent

    Joined:
    Apr 30, 2009
    Messages:
    6
    Hello

    I have some troubles in my design since i only want a thing to happend at the edge when the signal gets high, but insted it happens again and again while the signal is still high.

    Then I tried the this:

    Code:
    if blast'event and blast = '1' then
    
    I thought that I could use it on all signals but it seems that it only works on the clock? how can i solve it?


    Regards and thanks for your help and time!
     
    VHDLstudent, May 4, 2009
    #1
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  2. VHDLstudent

    jeppe

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    Mar 10, 2008
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    Denmark
    it should be ok -inside a process like:

    Process (Blast)
    begin
    if ....

    An alternative to your line could be

    if rising_edge( Blast) then ...
     
    jeppe, May 5, 2009
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  3. VHDLstudent

    VHDLstudent

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    I've tried that, but then I get this error:

    ERROR:Xst:827 - "C:/test.vhd" line 42: Signal signal_name cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

    It seems like my version of Xilinx doesn't support it? I Have the Student Version of Xilinx does that might course the problem?

    Thanx for your help so far.
     
    VHDLstudent, May 5, 2009
    #3
  4. VHDLstudent

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    How about if you generate a pulse that is one clock wide at the rising edge of blast? Something like this in a synchronous process:

    if (blast = "1") and (last_blast = "0") then
    blast_edge <= "1";
    else blast_edge <= "0";
    last_blast <= blast; -- previous clocks data

    Now you can use the state of blast_edge = "1" as your enable.
     
    JohnDuq, May 5, 2009
    #4
  5. VHDLstudent

    VHDLstudent

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    Messages:
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    Thanx for you answer JohnDug. I guess that could work too..

    But I just solved the problem by adding an extra state where I'm just setting the signal low again after one clock cyclus.

    Regards
     
    VHDLstudent, May 6, 2009
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