I can not figure this vhdl logic out, help.

Discussion in 'VHDL' started by logia, Jan 13, 2006.

  1. logia

    logia Guest

    Hi there,

    I have been read a piece of vhdl code and could not understand
    following part.
    My question is that regLoadEn = '1' only when both stLoadEn and
    qfnFingerEn
    are '1'. And all these statements are inside a PROCESS, which means
    they are
    executed in sequence. The second if statement will turn regLoadDone =
    '1' when
    regLoadEn = '1' and stLoadEn = '0'. But is this possible? Not, right?
    Because
    regLoadEn = '1' then stLoadEn must be '1'; if regLoadEn = '0' the
    second if
    statement will never be true. Therefore per following statements
    regLoadDone will
    never be '1'.

    Correct me if I am wrong. Thanks in advance!

    FingerInitClock :
    PROCESS ( crSysResetAX, sysDOFnDomClk )
    ...
    ...
    regLoadEn <= stLoadEn AND qfnFingerEn;

    IF (qfnFingerEn = '1') THEN


    -----------------------------------------------------------------------
    -- Falling Edge Detect

    -----------------------------------------------------------------------

    IF (regLoadEn = '1' AND stLoadEn = '0') THEN

    regLoadDone <= '1';

    ELSIF (stSymbolEn = '1' AND reg1stSymOnw = '0') THEN

    regLoadDone <= '0';

    END IF;

    ELSE

    regLoadDone <= '0';

    END IF;
    ....
    ....
    END PROCESS
    FingerInitClock;
    logia, Jan 13, 2006
    #1
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  2. logia

    jens Guest

    You left out an important part of the code, but the sensitivity list
    implies it's a synchronous process, and assuming the right conditions,
    regLoadDone will be '1' for one clock cycle after stLoadEn goes low.

    >And all these statements are inside a PROCESS, which means they are
    > executed in sequence.


    You might want to review how a process works, as that's not the case...
    (i.e. the
    "regLoadEn <= stLoadEn AND qfnFingerEn;"
    statement can be moved after
    "IF (qfnFingerEn = '1') THEN ... END IF;"
    and it would still work the same.
    jens, Jan 13, 2006
    #2
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  3. logia

    Dave Pollum Guest

    logia wrote:
    > Hi there,
    >
    > I have been read a piece of vhdl code and could not understand
    > following part.
    > My question is that regLoadEn = '1' only when both stLoadEn and
    > qfnFingerEn
    > are '1'. And all these statements are inside a PROCESS, which means
    > they are
    > executed in sequence. The second if statement will turn regLoadDone =
    > '1' when
    > regLoadEn = '1' and stLoadEn = '0'. But is this possible? Not, right?
    > Because
    > regLoadEn = '1' then stLoadEn must be '1'; if regLoadEn = '0' the
    > second if
    > statement will never be true. Therefore per following statements
    > regLoadDone will
    > never be '1'.
    >
    > Correct me if I am wrong. Thanks in advance!
    >
    > FingerInitClock :
    > PROCESS ( crSysResetAX, sysDOFnDomClk )
    > ...
    > ...
    > regLoadEn <= stLoadEn AND qfnFingerEn;
    >
    > IF (qfnFingerEn = '1') THEN
    >
    >
    > -----------------------------------------------------------------------
    > -- Falling Edge Detect
    >
    > -----------------------------------------------------------------------
    >
    > IF (regLoadEn = '1' AND stLoadEn = '0') THEN
    >
    > regLoadDone <= '1';
    >
    > ELSIF (stSymbolEn = '1' AND reg1stSymOnw = '0') THEN
    >
    > regLoadDone <= '0';
    >
    > END IF;
    >
    > ELSE
    >
    > regLoadDone <= '0';
    >
    > END IF;
    > ...
    > ...
    > END PROCESS
    > FingerInitClock;


    I'm guessing from the name that "sysDOFnDomClk" is the clock for the
    process. However, I don't see that it's used in the process. There
    are also several signals that should be in the process sensitivity
    list, such as reg1stSymOnw. If regLoadDone is supposed to be a
    register, the code is not correct for a synchronous process.
    -Dave Pollum
    Dave Pollum, Jan 13, 2006
    #3
  4. logia

    logia Guest

    Ok, I missed the ELSIF. I looked at online vhdl tutorial. It says
    statements are executed in order
    in process body. my understanding is that regLoadEn becomes '0' right
    away when DomClk = '1'
    and stLoadEn is '0'. Could you please explain a little bit more about
    what is really going on here?

    PROCESS

    ELSIF (sysDOFnDomClk'EVENT AND sysDOFnDomClk = '1') THEN

    regLoadEn <= stLoadEn AND qfnFingerEn;

    IF (qfnFingerEn = '1') THEN


    -----------------------------------------------------------------------
    -- Falling Edge Detect

    -----------------------------------------------------------------------

    IF (regLoadEn = '1' AND stLoadEn = '0') THEN

    regLoadDone <= '1';

    ELSIF (stSymbolEn = '1' AND reg1stSymOnw = '0') THEN

    regLoadDone <= '0';

    END IF;

    ELSE

    regLoadDone <= '0';

    END IF;
    END IF;

    END PROCESS
    jens wrote:

    >You left out an important part of the code, but the sensitivity list
    >implies it's a synchronous process, and assuming the right conditions,
    >regLoadDone will be '1' for one clock cycle after stLoadEn goes low.
    >
    >
    >
    >>And all these statements are inside a PROCESS, which means they are
    >> executed in sequence.
    >>
    >>

    >
    >You might want to review how a process works, as that's not the case...
    >(i.e. the
    >"regLoadEn <= stLoadEn AND qfnFingerEn;"
    >statement can be moved after
    >"IF (qfnFingerEn = '1') THEN ... END IF;"
    >and it would still work the same.
    >
    >
    >
    logia, Jan 13, 2006
    #4
  5. logia

    logia Guest

    The sensitive list is just like that. And the code is working. I did not
    post all the
    process code here, it's too long. All the other signals including
    regLoadEn are
    decleared in the architecture.

    Dave Pollum wrote:

    >
    >I'm guessing from the name that "sysDOFnDomClk" is the clock for the
    >process. However, I don't see that it's used in the process. There
    >are also several signals that should be in the process sensitivity
    >list, such as reg1stSymOnw. If regLoadDone is supposed to be a
    >register, the code is not correct for a synchronous process.
    >-Dave Pollum
    >
    >
    >
    logia, Jan 13, 2006
    #5
  6. logia

    backhus Guest


    > My question is that regLoadEn = '1' only when both
    > stLoadEn and qfnFingerEn are '1'. And all these statements are inside
    > a PROCESS, which means they are executed in sequence. The second if
    > statement will turn regLoadDone = '1' when regLoadEn = '1' and
    > stLoadEn = '0'. But is this possible? Not, right? Because regLoadEn =
    > '1' then stLoadEn must be '1'; if regLoadEn = '0' the second if
    > statement will never be true. Therefore per following statements
    > regLoadDone will never be '1'.
    >
    > Correct me if I am wrong. Thanks in advance!


    Hi logia.
    Signal values are only updated at the end of a process.
    (Reader-Driver Model of VHDL)

    This means: While the assignment places a '0' into the driver of
    regLoadEn a former '1' in the reader of that signal can still be
    evaluated in a following if-statement.

    The really confusing part is that the regLoadEn assignment is placed
    before the clocked part of the process. Due to the sensitivity list,
    this line will not be simulated unless clock or reset changes, but
    synthesis doesn't care about the sensitivity list. So.. will this line
    be synthesized into a register which is not explicitly written in the
    code or will it become a simple and gate? in the later case it could be
    written outside the process as a concurrent assignment. This again would
    affect the simulation.
    That's the real problem of this code.

    have a nice simulation
    Eilert
    backhus, Jan 16, 2006
    #6
  7. logia

    jens Guest

    > The really confusing part is that the regLoadEn assignment is placed
    > before the clocked part of the process. ...


    In post #3, a more complete version is shown and the regLoadEn
    assignment is inside the clocked part, so there is no confusion and
    simulation should match synthesis.

    I just noticed my previous post was incomplete... yes, in a clocked
    process statements are executed in order, but that is only for
    determining what the next value of a signal is. All signals are then
    simultaneously updated at the specified clock edge. So even though it
    may appear as if one signal assignment is immediately using the value
    of another signal assignment, that's not the case. From a hardware
    perspective, picture the output of one flip-flop going through some
    logic and then feeding into another flip-flop (that's what the process
    is doing- creating one flip-flop for every signal assignment). Note
    that variables are different, and the results would be much different
    if the process used variables.

    A good way to get more familiar with those concepts is to simulate (and
    make changes and see what they do).
    jens, Jan 16, 2006
    #7
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