Hi!
I have one question about IF condition and STD_LOGIC_VECTOR compatibillities. So, I try to compare two vectors: A and B. They are 32 bits long:
Process(...)
begin
..
IF (A <= B) THEN....
..
END IF;
..
end process;
Functions <=, <,... for the vectors is implemented in package "unsigned".
Multisim don't give any error, but this comparison just don't work. All logic is goot, just condition...Have you any thoughts?
Thanks
I have one question about IF condition and STD_LOGIC_VECTOR compatibillities. So, I try to compare two vectors: A and B. They are 32 bits long:
Process(...)
begin
..
IF (A <= B) THEN....
..
END IF;
..
end process;
Functions <=, <,... for the vectors is implemented in package "unsigned".
Multisim don't give any error, but this comparison just don't work. All logic is goot, just condition...Have you any thoughts?
Thanks