"IF" condition & STD_LOGIC_VECTOR

Discussion in 'VHDL' started by ontos, Jun 27, 2007.

  1. ontos

    ontos

    Joined:
    Mar 15, 2007
    Messages:
    12
    Hi!
    I have one question about IF condition and STD_LOGIC_VECTOR compatibillities. So, I try to compare two vectors: A and B. They are 32 bits long:

    Process(...)
    begin
    ..
    IF (A <= B) THEN....
    ..
    END IF;
    ..
    end process;

    Functions <=, <,... for the vectors is implemented in package "unsigned".
    Multisim don't give any error, but this comparison just don't work. All logic is goot, just condition...Have you any thoughts?

    Thanks
    ontos, Jun 27, 2007
    #1
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