Instance Name

Discussion in 'VHDL' started by ALuPin, Apr 7, 2005.

  1. ALuPin

    ALuPin Guest

    Hi newsgroup,

    is it ok when I use the name of a component for its instantiation ?
    Or do arise any confusing problems for the compiler when doing so ?

    Thank you for your help.

    Rgds
    André
    ALuPin, Apr 7, 2005
    #1
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  2. ALuPin

    Praveen Guest

    If you talking about somthing like this

    component andgate
    (
    );
    ....
    ...
    ...
    ....
    andgate : andgate port map (........................) ;
    ...
    ...

    yes, it will complain.
    Praveen, Apr 7, 2005
    #2
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  3. ALuPin

    ALuPin Guest

    "Praveen" <> wrote in message news:<>...
    > If you talking about somthing like this
    >
    > component andgate
    > (
    > );
    > ...
    > ..
    > ..
    > ...
    > andgate : andgate port map (........................) ;
    > ..
    > ..
    >
    > yes, it will complain.



    Yes, that is what I was talking about.

    Rgds
    André
    ALuPin, Apr 8, 2005
    #3
  4. ALuPin

    Eric DELAGE Guest

    > > andgate : andgate port map (........................) ;

    You should try the following:

    - put your component into a separate package P ;
    - add to your VHDL code
    ...
    use work.P;
    ...
    andgate: P.andgate port map (.....);
    ...

    This avoids the collision name issue and therefore should allow your
    instanciation. Please note that Synplify and ModelSim support this
    legal VHDL construct but Xilinx ISE not (or le's say that I haven't
    succeed to use it w/ XST ;-)

    Eric
    Eric DELAGE, Apr 8, 2005
    #4
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