VHDL Instance statement

[scs9gp]

Hi

I am new to VHDL and I have the following question:

I have an entity called PIPOReg which is simply a Parallel-Input Parallel Output register. I want to drop instances of this entity 'b' times in my design. How can I do this?

I am trying to do the following but it does not work perhaps because of the instance label C1, but the entity instantiation must have a label as far as I know.

In my design architecture I write the following as a data flow statement

GEN1: FOR v IN 1 TO b GENERATE
C1: ENTITY PIPOReg PORT MAP(clk,pin,pout);
END GENERATE GEN3;

I also tried to make a component of PIPOReg and instantiate the component but still that not the solution to the problem.

Thank you for your time
George

 

[scottcarl]

You need to declare the pin and pout signals as unique signals. Using an array of vectors should do it.

type p_type is array (1 to b) of std_logic_vector(15 downto 0);
signal pin, pout : p_type;

GEN1: FOR v IN 1 TO b GENERATE 
C1: ENTITY PIPOReg PORT MAP(clk,pin(v),pout(v));
END GENERATE GEN3;

Regards,
Scottcarl