Instances

Discussion in 'VHDL' started by XRay123, May 25, 2010.

  1. XRay123

    XRay123

    Joined:
    Mar 11, 2010
    Messages:
    6
    Hey guys.
    Is there any way to instantiate a component in VHDL without using all defining parameters (ports) ?
    For example having a component(clk, rst, data_in, data_out, merry_christmas) but when instancing to use it as component (clk, data_in, merry_christmas).
    Thanks for your time.
     
    XRay123, May 25, 2010
    #1
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  2. XRay123

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    you could do something like,
    Code:
    compMap: component port map( 
    clk => clk, 
    data_in => data_in, 
    data_out => [B]open[/B], 
    merry_christmas => merry_christmas);
    
     
    joris, May 26, 2010
    #2
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  3. XRay123

    XRay123

    Joined:
    Mar 11, 2010
    Messages:
    6
    Thank you. Message lengthened to more than 10 characters.
     
    XRay123, May 26, 2010
    #3
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