Instances

[XRay123]

Hey guys.
Is there any way to instantiate a component in VHDL without using all defining parameters (ports) ?
For example having a component(clk, rst, data_in, data_out, merry_christmas) but when instancing to use it as component (clk, data_in, merry_christmas).
Thanks for your time.

 

[joris]

you could do something like,

compMap: component port map( 
clk => clk, 
data_in => data_in, 
data_out => [B]open[/B], 
merry_christmas => merry_christmas);

 

[XRay123]

Thank you. Message lengthened to more than 10 characters.