integer range restriction

[Olaf]

Hi,

vhdl is very adventurously

Anyway, I wrote:

signal ts_count : std_ulogic_vector(31 downto 0);

counter: process (clk) is
constant LENGTH : positive := ts_count'length;
constant MAX_VALUE : positive := 2**LENGTH - 1;
...
begin

and got a runtime error from modelsim:

# ** Error: Value -1 is out of std.standard.positive range 1 to 2147483647.
# ** Error: Value -1 is out of std.standard.natural range 0 to 2147483647.

After some hours I found, that the ts_count vector is to long so that an
overflow of LENGTH/MAX_VALUE occurred ...

I need the MAX_VALUE since I need it to convert to gray code for further
use (generating an overflow signal).

Is there a way to use the full length of ts_count or other opportunities?

Thanks
Olaf

 

[swleegm]

Maybe, When LENGTH value is 0, MAX_VALUE is -1

Expected following?
constant LENGTH : positive := ts_count'length+1;

2^32 -1 : maximum tx_count's value.



Olaf :

 

[Olaf]

Hi,

vhdl is very adventurously

Anyway, I wrote:

signal ts_count : std_ulogic_vector(31 downto 0);

counter: process (clk) is
constant LENGTH : positive := ts_count'length;
constant MAX_VALUE : positive := 2**LENGTH - 1;
...
begin

and got a runtime error from modelsim:

# ** Error: Value -1 is out of std.standard.positive range 1 to 2147483647.
# ** Error: Value -1 is out of std.standard.natural range 0 to 2147483647.

After some hours I found, that the ts_count vector is to long so that an
overflow of LENGTH/MAX_VALUE occurred ...

Well, I found more informations on the Problem: There are strict LRM
requirements related to 32-bit integers. The LRM defines integer type as:

type INTEGER is range -2147483648 to 2147483647;

Consequently, assigning values greater than 2147483647 (16#7FFFFFFF# )
is illegal, for example:

signal s : integer:= 16#FFFFFFFF#;

doesn't work,

signal ts_count : std_ulogic_vector(30 downto 0);

for my case works.

VHDL Integers are represented as two's complement and type
postive/natural are subtypes - not helpfull here. 2^31 - 1 gives INT_MAX
= 2147483647.

Is there a work arround; e.g. for writing a counter bigger than 32 bit?
Some mikrocontroller e.g. does have 58-bit timestamp counters.

Thanks
Olaf

 

[Brian Drummond]

Well, I found more informations on the Problem: There are strict LRM
requirements related to 32-bit integers. The LRM defines integer type as:

type INTEGER is range -2147483648 to 2147483647;

Is there a work arround; e.g. for writing a counter bigger than 32 bit?
Some mikrocontroller e.g. does have 58-bit timestamp counters.

The numeric_std library contains both signed and unsigned types; use
whichever of these matches your application. Where values are within the
valid INTEGER range you can convert to and from [un]signed; but
normally, arithmetic between integer and numeric_std types is
straightforward

e.g.

my_40bit_counter_D <= my_40bit_counter_Q + 1;

- Brian

 

[Paul Uiterlinden]

Olaf wrote:

Well, I found more informations on the Problem: There are strict LRM
requirements related to 32-bit integers. The LRM defines integer type as:

type INTEGER is range -2147483648 to 2147483647;

No. The LRM specifies that the range is implementation dependent, but is
guaranteed to include the range -2147483647 to +2147483647. So
value -2147483648 (16#80000000) is missing. So you cannot convert vectors
larger than 31 bits to an integer type. Very awkward, IMHO.

Is there a work arround; e.g. for writing a counter bigger than 32 bit?
Some mikrocontroller e.g. does have 58-bit timestamp counters.

Use type unsigned from package ieee.numeric_std.

Example:

library ieee;
use ieee.numeric_std.all;
...
signal ts_count: unsigned(57 downto 0);
...
ts_count <= ts_count + 1;

 

[yves.770905]

Hi,

vhdl is very adventurously

Anyway, I wrote:

signal ts_count : std_ulogic_vector(31 downto 0);

counter: process (clk) is
constant LENGTH : positive := ts_count'length;
constant MAX_VALUE : positive := 2**LENGTH - 1;
...
begin

and got a runtime error from modelsim:

# ** Error: Value -1 is out of std.standard.positive range 1 to 2147483647.
# ** Error: Value -1 is out of std.standard.natural range 0 to 2147483647.

After some hours I found, that the ts_count vector is to long so that an
overflow of LENGTH/MAX_VALUE occurred ...

I need the MAX_VALUE since I need it to convert to gray code for further
use (generating an overflow signal).

Is there a way to use the full length of ts_count or other opportunities?

Thanks
Olaf

Olaf,

Is there any reason why MAX_VALUE should be of type positive?
If it is not required to have it as a type positive just define it
like this:

constant MAX_VALUE : std_ulogic_vector(ts_count'range) :=
(ts_count'range => '1');

Kind regards,

Yves

 

[Andy]

No. The LRM specifies that the range is implementation dependent, but is
guaranteed to include the range -2147483647 to +2147483647. So
value -2147483648 (16#80000000) is missing. So you cannot convert vectors
larger than 31 bits to an integer type. Very awkward, IMHO.


Use type unsigned from package ieee.numeric_std.

Example:

library ieee;
use ieee.numeric_std.all;
...
signal ts_count: unsigned(57 downto 0);
...
ts_count <= ts_count + 1;

Paul is correct in that the minimum supported range is 32 bits signed
(31 bits unsigned), but I do not know of any simulators that support
larger than the minimum range, which is extremely unfortunate.

Signed, 32 bit vectors can be converted to/from integer. Unsigned 32
bit vectors cannot (to/from natural).

I prefer the use of integers where possible, mostly for simulation
performance reasons. There are also areas where dealing with overflows
efficiently (in HW or simulation) is easier.

Andy

 

[Paul Uiterlinden]

Paul is correct in that the minimum supported range is 32 bits signed

Almost, except for that one value -2147483648.

Signed, 32 bit vectors can be converted to/from integer.

I don't want to sound pedantic, but 32 bit vectors can not be converted
to/from integer. At least not in a general and portable way, because that
one value is missing from the guaranteed range.