interconnecting two same type of components

Discussion in 'VHDL' started by deep, May 27, 2004.

  1. deep

    deep Guest

    I am trying to design a component that could be used multiple times. For ex
    C1 an c2. Now the ports of components are defined as :

    component c is(
    rst: in std_logic;
    clk : in std_logic;
    a: inout std_logic;
    b: inout std_logic);

    ...
    ...
    c1: c
    port map(
    rst=>rst,
    clk=>clk,
    a=> x, --a is output
    b=> y); --b is input

    c2: c
    port map(
    rst=>rst,
    clk=>clk,
    a=> y, --a is output
    b=> x);--a is output


    rst and clk are global input signals. "x" and "y" are used as wires
    interconnecting modules c1 and c2. "x" works as output of c1 and input of
    c2. "y" works as output of c2 and input of c1.c1 works in master mode and
    c2 works in slave mode. when asynchronous reset is applied, x is mapped as
    high. and then the operation starts subsequently with the logic applied.

    my problem is that "x" always remains at undefined level inspite of the
    fact that I forced it high when rst='1'. and same happens with "y" though
    it is derived after ther is some change on "x".

    I am synthesing the code in Xilinx and simulating on Modelsim.
    could somebody help me out .

    --deep
    deep, May 27, 2004
    #1
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  2. Hi deep,

    deep wrote:

    >I am trying to design a component that could be used multiple times. For ex
    >C1 an c2. Now the ports of components are defined as :
    >
    >component c is(
    > rst: in std_logic;
    > clk : in std_logic;
    > a: inout std_logic;
    > b: inout std_logic);
    >
    >

    You must banish usage of 'inout' into a sub-component. Inout are
    generally used at top chip level just before implementation of pad cells.

    More it miss some select signal to give directionality of the data.

    >..
    >..
    >c1: c
    >port map(
    > rst=>rst,
    > clk=>clk,
    > a=> x, --a is output
    > b=> y); --b is input
    >
    >
    >c2: c
    >port map(
    > rst=>rst,
    > clk=>clk,
    > a=> y, --a is output
    > b=> x);--a is output
    >
    >
    >rst and clk are global input signals. "x" and "y" are used as wires
    >interconnecting modules c1 and c2. "x" works as output of c1 and input of
    >c2. "y" works as output of c2 and input of c1.c1 works in master mode and
    >c2 works in slave mode. when asynchronous reset is applied, x is mapped as
    >high. and then the operation starts subsequently with the logic applied.
    >
    >my problem is that "x" always remains at undefined level inspite of the
    >fact that I forced it high when rst='1'. and same happens with "y" though
    >it is derived after ther is some change on "x".
    >
    >

    Read you implementation comments, in the both cells the 'x' is an
    output; you have two sources for the 'x' value, if you use a std_logic
    signal you have an undefined state.

    For 'y', you must give the code of 'c' component, but I suspect that you
    certainly have a sequential process to drive 'y', something like:

    process (clk)
    if (clk'event and clk=1) then
    b <= f(a);
    end if;

    then event on 'x' doesn't drive event on 'b'

    Or see my remark on missing ports.
    If you have no logic which give the sens of the 'a' and 'b' value, the
    circuit can't resolve the values.

    Remember: inside a chip level, all internal signals must be
    monodirectional to ensure logic resolution. Take as example a AND gate
    where you connect the output as input, that give you a deadlock
    situation, if any others inputs go to logical '0'.

    JaI
    Just an Illusion, Jun 8, 2004
    #2
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