Verilog Counter Question

Discussion in 'VHDL' started by e.hanrahan27@gmail.com, Nov 10, 2012.

  1. Guest

    Hi I am very new to digital design and am using Verilog to code some modules.
    The following is the module code for a Counter I designed using Verilog.

    //
    module counter (clk,rst,q);
    input clk,rst;
    output [2:0] q;
    reg [2:0] q;

    always @ (posedge clk)
    begin
    if (rst==0)
    q <= 0;
    else
    q <= q+1;
    end
    endmodule
    //

    In the testbench I set (rst = 0) for the first 10ns and then (rst = 1) for the rest. The following is the testbench code.

    module countertest;
    reg clk, rst;
    wire q;

    counter c1(clk,rst,q);

    //
    always
    begin
    #5 clk = ~clk;
    end

    initial
    begin
    clk = 0;
    rst = 0;
    #10 rst =1;
    end
    endmodule
    //

    my question is this - what does the command (q <= q + 1) do in this example. The simulation shows that it will start to cause the q output to cycle between low and high every 10ns. I want to know why this is?
     
    , Nov 10, 2012
    #1
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  2. Le 10/11/2012 19:41, a écrit :
    > Hi I am very new to digital design and am using Verilog to code some modules.
    > The following is the module code for a Counter I designed using Verilog.


    So why do you ask your question in the VHDL group ? ;o)

    Nicolas
     
    Nicolas Matringe, Nov 10, 2012
    #2
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  3. Gabor Guest

    On 11/10/2012 1:41 PM, wrote:
    > Hi I am very new to digital design and am using Verilog to code some modules.
    > The following is the module code for a Counter I designed using Verilog.
    >
    > //
    > module counter (clk,rst,q);
    > input clk,rst;
    > output [2:0] q;
    > reg [2:0] q;
    >
    > always @ (posedge clk)
    > begin
    > if (rst==0)
    > q <= 0;
    > else
    > q <= q+1;
    > end
    > endmodule
    > //
    >
    > In the testbench I set (rst = 0) for the first 10ns and then (rst = 1) for the rest. The following is the testbench code.
    >
    > module countertest;
    > reg clk, rst;
    > wire q;
    >
    > counter c1(clk,rst,q);
    >
    > //
    > always
    > begin
    > #5 clk = ~clk;
    > end
    >
    > initial
    > begin
    > clk = 0;
    > rst = 0;
    > #10 rst =1;
    > end
    > endmodule
    > //
    >
    > my question is this - what does the command (q <= q + 1) do in this example. The simulation shows that it will start to cause the q output to cycle between low and high every 10ns. I want to know why this is?
    >

    As pointed out, there is a Verilog newsgroup.

    As to your question, q in the counter module is a three bit
    vector. q in the test bench is a single wire. In Verilog, it
    is not an error (but you should have seen a warning) to connect
    a wire to a port that does not match the width of the wire. So
    in your case q from the test bench just shows the LSB of the
    counter, which would toggle on each rising clock edge.

    -- Gabor
     
    Gabor, Nov 11, 2012
    #3
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