verilog

Discussion in 'VHDL' started by umamahe, Nov 5, 2012.

  1. umamahe

    umamahe

    Joined:
    Nov 5, 2012
    Messages:
    1
    i'm trying to write a program for different led pattern using verilog.But i dont know why loop statement are not executed.this is my program

    module led_p(led,clk);
    output [7:0] led;
    input clk;
    reg[7:0] t;
    reg [7:0] led;
    always @(posedge clk) begin
    repeat(10)
    begin
    t=8'b00000001;
    t= t<<1 ;
    end
    led[7:0]=t;
    end
    endmodule
    umamahe, Nov 5, 2012
    #1
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