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Hey all, I just discovered these forums today and saw how many people have been helped with questions. My class just jumped into VHDL recently and i've been struggling with the first assignment and with two more on the way I really need to learn this stuff.
I checked out The Student's Guide to VHDL recently and its helping a bit.
The first assignment involves building the vhdl model of 74LVQ163
stmicroelectronics.com/stonline/books/pdf/docs/8079.pdf
Its a 4-bit presettable counter. Were supposed to be just getting the hang of VHDL by implementing this based off of a basic counter which he gave the code for, as well as writing a test bench. Theres a truth table in the pdf file to code the processes off of but im not sure where to start.
Im trying to dissect this code to rebuild it as a 4 bit counter and slightly understand how to set the code to read the clear to reset the counter but not enough to build the code for the counting, nor do I understand the cases in the process at the bottom. The assignment is already due, and hes posting the next one today so I wanted to fully understand what we had to do before moving on. All im looking for is help on how I should be going about understanding this and how im supposed to be coding it as well as any other resources (like tutorials) on how to write this language. Thanks in advance for any help. This seems pretty easy, im slightly embarrassed that I'm so lost
I checked out The Student's Guide to VHDL recently and its helping a bit.
The first assignment involves building the vhdl model of 74LVQ163
stmicroelectronics.com/stonline/books/pdf/docs/8079.pdf
Its a 4-bit presettable counter. Were supposed to be just getting the hang of VHDL by implementing this based off of a basic counter which he gave the code for, as well as writing a test bench. Theres a truth table in the pdf file to code the processes off of but im not sure where to start.
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity basic_cnt is
port(
clock, sel, a, b : in STD_LOGIC;
reset : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR(3 downto 0);
q: out std_logic
);
end basic_cnt;
architecture basic_cnt_arch of basic_cnt is
signal Qint: STD_LOGIC_VECTOR (3 downto 0);
signal s: std_logic;
begin
process (clock, reset)
begin
if reset ='1' then
Qint <= "0000";
else
if clock'event and clock = '1' then
if Qint<"1001" then
Qint<=Qint + '1';
else
Qint<="0000";
end if;
end if;
end if;
end process;
Qout <= Qint;
process (sel, a, b)
begin
s <= sel;
case s is
when '0' => q <= a;
when '1' => q <= b;
when others => q <= 'X';
end case;
end process;
end basic_cnt_arch;
Im trying to dissect this code to rebuild it as a 4 bit counter and slightly understand how to set the code to read the clear to reset the counter but not enough to build the code for the counting, nor do I understand the cases in the process at the bottom. The assignment is already due, and hes posting the next one today so I wanted to fully understand what we had to do before moving on. All im looking for is help on how I should be going about understanding this and how im supposed to be coding it as well as any other resources (like tutorials) on how to write this language. Thanks in advance for any help. This seems pretty easy, im slightly embarrassed that I'm so lost