Is it possible to infer double data rate registers from VHDL code?

Discussion in 'VHDL' started by bwilson79@gmail.com, Aug 10, 2007.

  1. Guest

    I couldn't really find anything in both the Xilinx XST user guide or
    the Synplicity user guide. I tried several different approaches and
    synthesized with Synplify Pro 8.8.0.4 and it's not working.
     
    , Aug 10, 2007
    #1
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  2. "" <> writes:

    > I couldn't really find anything in both the Xilinx XST user guide or
    > the Synplicity user guide. I tried several different approaches and
    > synthesized with Synplify Pro 8.8.0.4 and it's not working.


    Check the Xilinx website - IIRC the way to do this is to instanciate
    specific cells from a xilinx technology library.


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
     
    Kai Harrekilde-Petersen, Aug 11, 2007
    #2
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  3. I believe that for Xilinx parts, any double data
    rate is handled at the IO ports with ISERDES and
    OSERDES primitives. To gain speed, an input ISERDES
    will have two pairs of shift registers, one clocked
    at the positive edge, one at the negative. The logic
    values are then latched into an output register on
    a clock that represents a "framing" rate.

    In the fabric, data is moved along on either negative
    or positive edges, but I think not both. You might
    get your simulator tool to handle the inference of
    a dual edge data transfer, but the Xilinx synthesis
    tool will give you an error.

    Brad Smallridge
    Ai Vision
     
    Brad Smallridge, Aug 12, 2007
    #3
  4. Andy Guest

    On Aug 12, 4:33 pm, "Brad Smallridge" <>
    wrote:
    > I believe that for Xilinx parts, any double data
    > rate is handled at the IO ports with ISERDES and
    > OSERDES primitives. To gain speed, an input ISERDES
    > will have two pairs of shift registers, one clocked
    > at the positive edge, one at the negative. The logic
    > values are then latched into an output register on
    > a clock that represents a "framing" rate.
    >
    > In the fabric, data is moved along on either negative
    > or positive edges, but I think not both. You might
    > get your simulator tool to handle the inference of
    > a dual edge data transfer, but the Xilinx synthesis
    > tool will give you an error.
    >
    > Brad Smallridge
    > Ai Vision


    In Xilinx and Altera, DDR is handled in the IOB, but not necessarily
    with ISERDES/OSERDES (i.e. DDR is supported in devices with no ISERDES/
    OSERDES capability). There are two connections to the fabric,
    representing the data from/for both edges. The data streams are
    typically handled separately in the fabric, or can be handled as one
    with a 2x clock.

    There is a separate discussion going on about the desired ability to
    infer DDR circuits within the fabric that consist of only SDR flops
    and combinatorial logic (and are described in RTL as being DDR). I
    don't know why it is not used more often, but in practical terms, if
    you have a DLL/PLL clock manager, creating a 2x clock and processing
    the data internally at that rate is easier and more efficient in most
    applications. Still, there is the odd case of a non-uniform clock,
    etc. where doubling the clock is not feasible, and such circuits would
    be desirable.

    Andy
     
    Andy, Aug 14, 2007
    #4
  5. beckjer Guest

    While not a strict DDR implementation, I have found in my designs
    (Altera, I haven't tried on Xilinx) that using 1 process per edge
    seems to work. Granted it is more a read on falling edge, write on
    rising edge system, but so far it's working well. My system is a
    parallel interface, ~30nS clock cycle.

    I use
    process (clk)
    begin
    wait until rising_edge(clk);
    ....
    end process;

    process (clk)
    begin
    wait until falling_edge(clk);
    ....
    end process;

    It simulates in Modelsim with no problems (that I have seen), and the
    protoboard appears to work when attached to the actual hardware.
     
    beckjer, Aug 15, 2007
    #5
  6. Jim Lewis Guest

    Re: Is it possible to infer double data rate registers from VHDLcode?

    wrote:
    > I couldn't really find anything in both the Xilinx XST user guide or
    > the Synplicity user guide. I tried several different approaches and
    > synthesized with Synplify Pro 8.8.0.4 and it's not working.


    In the VHDL RTL Synthesis Standard (1076.6-2004), the coding style is:

    DualEdge_Proc: process (Clk, Reset) is
    begin
    if Reset = '1' then
    Q <= (others => '0');
    elsif rising_edge(Clk) then
    Q <= D4Rise;
    elsif falling_edge(Clk) then
    Q <= D4Fall;
    end if;
    end process DualEdge_Proc;


    For different clocks:
    process( reset, clk1, clk2 )
    begin
    if reset = '1' then
    Q <= '0' ;
    elsif rising_edge(clk1) then
    Q <= data1 ;
    elsif rising_edge(clk2) then
    Q <= data2 ;
    end if ;
    end process ;

    While this may not currently work, it does give you a standard
    to reference when you file a bug report with your vendors.

    I do note there is a coding style in Xilinx that uses shared
    variables, however, their usage of shared variables is illegal
    in VHDL-2002.

    Cheers,
    Jim
    SynthWorks VHDL Training
     
    Jim Lewis, Aug 16, 2007
    #6
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