I believe that for Xilinx parts, any double data
rate is handled at the IO ports with ISERDES and
OSERDES primitives. To gain speed, an input ISERDES
will have two pairs of shift registers, one clocked
at the positive edge, one at the negative. The logic
values are then latched into an output register on
a clock that represents a "framing" rate.
In the fabric, data is moved along on either negative
or positive edges, but I think not both. You might
get your simulator tool to handle the inference of
a dual edge data transfer, but the Xilinx synthesis
tool will give you an error.
Brad Smallridge
Ai Vision
In Xilinx and Altera, DDR is handled in the IOB, but not necessarily
with ISERDES/OSERDES (i.e. DDR is supported in devices with no ISERDES/
OSERDES capability). There are two connections to the fabric,
representing the data from/for both edges. The data streams are
typically handled separately in the fabric, or can be handled as one
with a 2x clock.
There is a separate discussion going on about the desired ability to
infer DDR circuits within the fabric that consist of only SDR flops
and combinatorial logic (and are described in RTL as being DDR). I
don't know why it is not used more often, but in practical terms, if
you have a DLL/PLL clock manager, creating a 2x clock and processing
the data internally at that rate is easier and more efficient in most
applications. Still, there is the odd case of a non-uniform clock,
etc. where doubling the clock is not feasible, and such circuits would
be desirable.
Andy