Is this Code synthesizable and any suggestions

Discussion in 'VHDL' started by Rama, Jan 13, 2007.

  1. Rama

    Rama Guest

    I have a question for the synthesis experts out there. I am a novice in
    this area and am more of a functional verification person.

    However, here is a piece pf VHDL code - that i have and works fine in
    the simulation world.

    However, when I program this same code onto thr FPGA - Xilinix ISE - I
    don't see what I should be seeing ( was expecting the clock to turn off
    )
    The point of this piece of code was --
    at time 0 --- have a default setup
    wait for certain clock cycles -- reset the PLL
    wait for some more clock cycles -- Reset the DSP
    wait for some more clock cycles -- Then Shut the CLOCK off - the DSP
    clock here.

    I tried doing the above -- in the code below.

    This works in the simulation -- I do see the expected result i.e

    I want to see the FPGA_MIZER_CLK - shut down after certain clock cycles
    and after the DSP is reset. So i tried doing the sequence I need to
    like this..

    The question is ----- Is this synthesizable ?

    What are the pitfalls ?

    (if you see I also have a counter and it is just counting
    continuously....)

    I would like suggestions if there's different ways of doing the same
    here.

    Thanks,
    RC

    =============================

    I/O's declaration...

    FPGA_PLL_RESETN : out std_logic;
    FPGA_PLL_SCLK : out std_logic;
    FPGA_PLL_SCLK_SEL : out std_logic;
    FPGA_MIZER_CLK : out std_logic;
    FPGA_PLL_SIN : out std_logic;
    FPGA_PLL_SEN : out std_logic;
    FPGA_PLL_LD : out std_logic;

    FPGA_TRSTN : out std_logic;
    FPGA_SCAN_EN : out std_logic;
    FPGA_DSP_N : out std_logic;

    ......
    ......CLK26MHZ : in std_logic;


    architecture behavioral ...
    begin
    signal MISER_PLL_RESETN : std_logic := '0' ;
    signal MIZER_CLK : std_logic := '0' ;
    signal MISER_DSP_N : std_logic := '0';
    signal MISER_CLKOFF : std_logic :='0';
    signal COUNT1 : integer :=0;

    ....
    ....
    ...

    miser_control : process ( CLK26MHZ )
    begin

    MIZER_CLK <= CLK26MHZ;
    if rising_edge ( CLK26MHZ ) then
    COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    end if;

    end process;

    process ( COUNT1 )
    begin
    if ( COUNT1 >= 50 ) THEN -- e_pll_resetn - goes high after 50 clk
    cycles
    MISER_PLL_RESETN<='1';
    end if;
    if ( COUNT1 >= 100 ) THEN
    MISER_PLL_RESETN <='0';
    end if;
    if ( COUNT1 >= 150 ) THEN
    MISER_DSP_N <= '1';
    end if;
    end process;

    process ( MISER_DSP_N, COUNT1)
    begin
    -- enabling Clock Off
    if ( MISER_DSP_N = '1' ) THEN
    if ( COUNT1 >= 200 ) THEN
    MISER_CLKOFF <= '1';
    end if;
    if ( COUNT1 <= 250 ) THEN
    MISER_CLKOFF <= '0';
    end if;

    end if;

    end process;

    FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    '0' when ( MISER_CLKOFF = '1' ) else
    '0';

    FPGA_PLL_RESETN<= MISER_PLL_RESETN ;
    FPGA_DSP_N <= MISER_DSP_N ;

    end behavioral;
     
    Rama, Jan 13, 2007
    #1
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  2. Rama

    Guest

    I doubt this is synthesizable. Although there's no hard definition of
    synthesizable short of what your tool vendor tells you,
    IEEE-1076.6-2004 talks about a normal set of coding styles and
    structures for synthesis. If you want a synchronous process (and what
    good designer doesn't :), you need to stick to a pretty conservative
    definition of clock (i.e. using rising_edge() or clk'event and clk='1'
    style). Further, if you want to use a process with multiple wait
    statements, the spec I mentioned (in clause 6.1.3.4 requires that "each
    wait statement shall specify the same clock edge of a single clock").
    If you don't want a synchronous process, all wait conditions must use
    the same, identical async_condition.

    It's unfortunate, but once you start enjoying the ease of designing
    simulation-only testbench code, you get kind of locked into staying in
    simulation.

    HTH,

    - Kenn

    Rama wrote:
    > I have a question for the synthesis experts out there. I am a novice in
    > this area and am more of a functional verification person.
    >
    > However, here is a piece pf VHDL code - that i have and works fine in
    > the simulation world.
    >
    > However, when I program this same code onto thr FPGA - Xilinix ISE - I
    > don't see what I should be seeing ( was expecting the clock to turn off
    > )
    > The point of this piece of code was --
    > at time 0 --- have a default setup
    > wait for certain clock cycles -- reset the PLL
    > wait for some more clock cycles -- Reset the DSP
    > wait for some more clock cycles -- Then Shut the CLOCK off - the DSP
    > clock here.
    >
    > I tried doing the above -- in the code below.
    >
    > This works in the simulation -- I do see the expected result i.e
    >
    > I want to see the FPGA_MIZER_CLK - shut down after certain clock cycles
    > and after the DSP is reset. So i tried doing the sequence I need to
    > like this..
    >
    > The question is ----- Is this synthesizable ?
    >
    > What are the pitfalls ?
    >
    > (if you see I also have a counter and it is just counting
    > continuously....)
    >
    > I would like suggestions if there's different ways of doing the same
    > here.
    >
    > Thanks,
    > RC
    >
    > =============================
    >
    > I/O's declaration...
    >
    > FPGA_PLL_RESETN : out std_logic;
    > FPGA_PLL_SCLK : out std_logic;
    > FPGA_PLL_SCLK_SEL : out std_logic;
    > FPGA_MIZER_CLK : out std_logic;
    > FPGA_PLL_SIN : out std_logic;
    > FPGA_PLL_SEN : out std_logic;
    > FPGA_PLL_LD : out std_logic;
    >
    > FPGA_TRSTN : out std_logic;
    > FPGA_SCAN_EN : out std_logic;
    > FPGA_DSP_N : out std_logic;
    >
    > .....
    > .....CLK26MHZ : in std_logic;
    >
    >
    > architecture behavioral ...
    > begin
    > signal MISER_PLL_RESETN : std_logic := '0' ;
    > signal MIZER_CLK : std_logic := '0' ;
    > signal MISER_DSP_N : std_logic := '0';
    > signal MISER_CLKOFF : std_logic :='0';
    > signal COUNT1 : integer :=0;
    >
    > ...
    > ...
    > ..
    >
    > miser_control : process ( CLK26MHZ )
    > begin
    >
    > MIZER_CLK <= CLK26MHZ;
    > if rising_edge ( CLK26MHZ ) then
    > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > end if;
    >
    > end process;
    >
    > process ( COUNT1 )
    > begin
    > if ( COUNT1 >= 50 ) THEN -- e_pll_resetn - goes high after 50 clk
    > cycles
    > MISER_PLL_RESETN<='1';
    > end if;
    > if ( COUNT1 >= 100 ) THEN
    > MISER_PLL_RESETN <='0';
    > end if;
    > if ( COUNT1 >= 150 ) THEN
    > MISER_DSP_N <= '1';
    > end if;
    > end process;
    >
    > process ( MISER_DSP_N, COUNT1)
    > begin
    > -- enabling Clock Off
    > if ( MISER_DSP_N = '1' ) THEN
    > if ( COUNT1 >= 200 ) THEN
    > MISER_CLKOFF <= '1';
    > end if;
    > if ( COUNT1 <= 250 ) THEN
    > MISER_CLKOFF <= '0';
    > end if;
    >
    > end if;
    >
    > end process;
    >
    > FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    > '0' when ( MISER_CLKOFF = '1' ) else
    > '0';
    >
    > FPGA_PLL_RESETN<= MISER_PLL_RESETN ;
    > FPGA_DSP_N <= MISER_DSP_N ;
    >
    > end behavioral;
     
    , Jan 15, 2007
    #2
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  3. Hi,

    Rama schrieb:

    > The question is ----- Is this synthesizable ?


    Not really.

    > What are the pitfalls ?


    See below

    > signal MISER_PLL_RESETN : std_logic := '0' ;
    > signal MIZER_CLK : std_logic := '0' ;
    > signal MISER_DSP_N : std_logic := '0';
    > signal MISER_CLKOFF : std_logic :='0';
    > signal COUNT1 : integer :=0;


    A default value for a signal is not synthesisable. In general you need
    a reset to set all FF in a default value. But this is OK for Xilinx
    fpgas and should synthesis perfect.


    > miser_control : process ( CLK26MHZ )
    > MIZER_CLK <= CLK26MHZ;
    > if rising_edge ( CLK26MHZ ) then
    > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > end if;


    This is impossible. Mizer_Clk would need a FF reacting on both clock
    edges which is not available.
    But it should be ok to move this line out of the process as a
    concurrent statement.

    > process ( COUNT1 )


    This process inferrs two latches.

    > process ( MISER_DSP_N, COUNT1)


    This process inferrs one latch.

    I don't think your really want latches, so you should write out all
    else cases in a combinatorial process in order to avoid a latch.

    bye Thomas
     
    Thomas Stanka, Jan 15, 2007
    #3
  4. Rama

    Rama Guest

    Thank you so much for the good feedback Thomans and Kenn.
    Yes I did think that was the case -- that it was not synthesizable -
    and I was guessing about the inference of latches too - however was not
    sure -

    Okay - thinking about this whole - sequence How about if I just put the
    delays in there...as I know for sure I will be getting a 38.46 ns -
    Clock ( 26 Mhz )

    How about like this -- for experimental purposes to see if the Clock is
    really turning off.

    -- miser : 01/15/07 - rc

    MIZER_CLK <= CLK26MHZ;

    MISER_PLL_RESETN <= '0' ,
    '1' after 1923 ns, -- 50 clks of 38.46 ns period
    '0' after 3846 ns; -- 100 clks of 38.46 ns period

    MISER_DSP_N <= '0',
    '1' after 5769 ns; -- 150 clks of 38.46 ns

    MISER_CLKOFF <= '0',
    '1' after 1923 ns when (MISER_DSP_N ='1') else -- 50 clks from
    time DSP-reset is high
    '0' after 3846 ns when (MISER_DSP_N ='1') ; -- 100 clks from
    DSP_RESET is high

    FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    '0' when ( MISER_CLKOFF = '1' ) else -- do I need else here ? can
    I end here?
    '0';



    Thanks a lot for your time !

    Regards,
    Rama


    On Jan 15, 3:26 am, "Thomas Stanka" <> wrote:
    > Hi,
    >
    > Rama schrieb:
    >
    > > The question is ----- Is this synthesizable ?Not really.

    >
    > > What are the pitfalls ?See below

    >
    > > signal MISER_PLL_RESETN : std_logic := '0' ;
    > > signal MIZER_CLK : std_logic := '0' ;
    > > signal MISER_DSP_N : std_logic := '0';
    > > signal MISER_CLKOFF : std_logic :='0';
    > > signal COUNT1 : integer :=0;A default value for a signal is not synthesisable. In general you need

    > a reset to set all FF in a default value. But this is OK for Xilinx
    > fpgas and should synthesis perfect.
    >
    > > miser_control : process ( CLK26MHZ )
    > > MIZER_CLK <= CLK26MHZ;
    > > if rising_edge ( CLK26MHZ ) then
    > > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > > end if;This is impossible. Mizer_Clk would need a FF reacting on both clock

    > edges which is not available.
    > But it should be ok to move this line out of the process as a
    > concurrent statement.
    >
    > > process ( COUNT1 )This process inferrs two latches.

    >
    > > process ( MISER_DSP_N, COUNT1)This process inferrs one latch.

    >
    > I don't think your really want latches, so you should write out all
    > else cases in a combinatorial process in order to avoid a latch.
    >
    > bye Thomas
     
    Rama, Jan 15, 2007
    #4
  5. Rama wrote:

    > Okay - thinking about this whole - sequence How about if I just put the
    > delays in there...as I know for sure I will be getting a 38.46 ns -
    > Clock ( 26 Mhz )


    How about following some sort of synchronous template:

    one : process(reset, clock) is
    -- <Process declarations here>
    begin
    if reset = '1' then
    init_regs_here;
    elsif rising_edge(clock) then
    update_regs_here;
    end if;
    update_ports_here;
    end process one;


    -- Mike Treseler
     
    Mike Treseler, Jan 15, 2007
    #5
  6. Rama

    Andy Guest

    Your code will generate a synchronous counter (good).
    But it will generate combinatorially decoded outputs (potentially bad;
    they will be glitchy).

    I would suggest you decode your outputs in the same process as the
    counter, so they will be synchronous (registered) too, and not have
    glitches which could cause problems elsewhere (especially if the resets
    are used asynchronously).

    Also, by coding everything in clocked process(es), you avoid the
    possibility of latches which are "a bad thing".

    Andy


    Rama wrote:
    > I have a question for the synthesis experts out there. I am a novice in
    > this area and am more of a functional verification person.
    >
    > However, here is a piece pf VHDL code - that i have and works fine in
    > the simulation world.
    >
    > However, when I program this same code onto thr FPGA - Xilinix ISE - I
    > don't see what I should be seeing ( was expecting the clock to turn off
    > )
    > The point of this piece of code was --
    > at time 0 --- have a default setup
    > wait for certain clock cycles -- reset the PLL
    > wait for some more clock cycles -- Reset the DSP
    > wait for some more clock cycles -- Then Shut the CLOCK off - the DSP
    > clock here.
    >
    > I tried doing the above -- in the code below.
    >
    > This works in the simulation -- I do see the expected result i.e
    >
    > I want to see the FPGA_MIZER_CLK - shut down after certain clock cycles
    > and after the DSP is reset. So i tried doing the sequence I need to
    > like this..
    >
    > The question is ----- Is this synthesizable ?
    >
    > What are the pitfalls ?
    >
    > (if you see I also have a counter and it is just counting
    > continuously....)
    >
    > I would like suggestions if there's different ways of doing the same
    > here.
    >
    > Thanks,
    > RC
    >
    > =============================
    >
    > I/O's declaration...
    >
    > FPGA_PLL_RESETN : out std_logic;
    > FPGA_PLL_SCLK : out std_logic;
    > FPGA_PLL_SCLK_SEL : out std_logic;
    > FPGA_MIZER_CLK : out std_logic;
    > FPGA_PLL_SIN : out std_logic;
    > FPGA_PLL_SEN : out std_logic;
    > FPGA_PLL_LD : out std_logic;
    >
    > FPGA_TRSTN : out std_logic;
    > FPGA_SCAN_EN : out std_logic;
    > FPGA_DSP_N : out std_logic;
    >
    > .....
    > .....CLK26MHZ : in std_logic;
    >
    >
    > architecture behavioral ...
    > begin
    > signal MISER_PLL_RESETN : std_logic := '0' ;
    > signal MIZER_CLK : std_logic := '0' ;
    > signal MISER_DSP_N : std_logic := '0';
    > signal MISER_CLKOFF : std_logic :='0';
    > signal COUNT1 : integer :=0;
    >
    > ...
    > ...
    > ..
    >
    > miser_control : process ( CLK26MHZ )
    > begin
    >
    > MIZER_CLK <= CLK26MHZ;
    > if rising_edge ( CLK26MHZ ) then
    > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > end if;
    >
    > end process;
    >
    > process ( COUNT1 )
    > begin
    > if ( COUNT1 >= 50 ) THEN -- e_pll_resetn - goes high after 50 clk
    > cycles
    > MISER_PLL_RESETN<='1';
    > end if;
    > if ( COUNT1 >= 100 ) THEN
    > MISER_PLL_RESETN <='0';
    > end if;
    > if ( COUNT1 >= 150 ) THEN
    > MISER_DSP_N <= '1';
    > end if;
    > end process;
    >
    > process ( MISER_DSP_N, COUNT1)
    > begin
    > -- enabling Clock Off
    > if ( MISER_DSP_N = '1' ) THEN
    > if ( COUNT1 >= 200 ) THEN
    > MISER_CLKOFF <= '1';
    > end if;
    > if ( COUNT1 <= 250 ) THEN
    > MISER_CLKOFF <= '0';
    > end if;
    >
    > end if;
    >
    > end process;
    >
    > FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    > '0' when ( MISER_CLKOFF = '1' ) else
    > '0';
    >
    > FPGA_PLL_RESETN<= MISER_PLL_RESETN ;
    > FPGA_DSP_N <= MISER_DSP_N ;
    >
    > end behavioral;
     
    Andy, Jan 16, 2007
    #6
  7. Rama

    Rama Guest

    All,

    thank you so much. You have given me good insight about synthesis.
    Yes you get locked into simulation mode TB's -- once you begin writing
    sim TB's.

    I had one more question on how to write this equvalent synthesizable
    code for this one statement -

    I had written a synchronous counter ( with synchronous reset internal
    to the counter )

    count_test : count1 ( clk => CLK26MHZ,
    reset => reset,
    cntout => CNT_OUT );

    If I were to do this statement's equivalent code now --- How would I do
    this in synthesis code of VHDL ? Any ideas/suggestions ?

    MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else
    '0' ;

    Thanks much.


    Andy wrote:
    > Your code will generate a synchronous counter (good).
    > But it will generate combinatorially decoded outputs (potentially bad;
    > they will be glitchy).
    >
    > I would suggest you decode your outputs in the same process as the
    > counter, so they will be synchronous (registered) too, and not have
    > glitches which could cause problems elsewhere (especially if the resets
    > are used asynchronously).
    >
    > Also, by coding everything in clocked process(es), you avoid the
    > possibility of latches which are "a bad thing".
    >
    > Andy
    >
    >
    > Rama wrote:
    > > I have a question for the synthesis experts out there. I am a novice in
    > > this area and am more of a functional verification person.
    > >
    > > However, here is a piece pf VHDL code - that i have and works fine in
    > > the simulation world.
    > >
    > > However, when I program this same code onto thr FPGA - Xilinix ISE - I
    > > don't see what I should be seeing ( was expecting the clock to turn off
    > > )
    > > The point of this piece of code was --
    > > at time 0 --- have a default setup
    > > wait for certain clock cycles -- reset the PLL
    > > wait for some more clock cycles -- Reset the DSP
    > > wait for some more clock cycles -- Then Shut the CLOCK off - the DSP
    > > clock here.
    > >
    > > I tried doing the above -- in the code below.
    > >
    > > This works in the simulation -- I do see the expected result i.e
    > >
    > > I want to see the FPGA_MIZER_CLK - shut down after certain clock cycles
    > > and after the DSP is reset. So i tried doing the sequence I need to
    > > like this..
    > >
    > > The question is ----- Is this synthesizable ?
    > >
    > > What are the pitfalls ?
    > >
    > > (if you see I also have a counter and it is just counting
    > > continuously....)
    > >
    > > I would like suggestions if there's different ways of doing the same
    > > here.
    > >
    > > Thanks,
    > > RC
    > >
    > > =============================
    > >
    > > I/O's declaration...
    > >
    > > FPGA_PLL_RESETN : out std_logic;
    > > FPGA_PLL_SCLK : out std_logic;
    > > FPGA_PLL_SCLK_SEL : out std_logic;
    > > FPGA_MIZER_CLK : out std_logic;
    > > FPGA_PLL_SIN : out std_logic;
    > > FPGA_PLL_SEN : out std_logic;
    > > FPGA_PLL_LD : out std_logic;
    > >
    > > FPGA_TRSTN : out std_logic;
    > > FPGA_SCAN_EN : out std_logic;
    > > FPGA_DSP_N : out std_logic;
    > >
    > > .....
    > > .....CLK26MHZ : in std_logic;
    > >
    > >
    > > architecture behavioral ...
    > > begin
    > > signal MISER_PLL_RESETN : std_logic := '0' ;
    > > signal MIZER_CLK : std_logic := '0' ;
    > > signal MISER_DSP_N : std_logic := '0';
    > > signal MISER_CLKOFF : std_logic :='0';
    > > signal COUNT1 : integer :=0;
    > >
    > > ...
    > > ...
    > > ..
    > >
    > > miser_control : process ( CLK26MHZ )
    > > begin
    > >
    > > MIZER_CLK <= CLK26MHZ;
    > > if rising_edge ( CLK26MHZ ) then
    > > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > > end if;
    > >
    > > end process;
    > >
    > > process ( COUNT1 )
    > > begin
    > > if ( COUNT1 >= 50 ) THEN -- e_pll_resetn - goes high after 50 clk
    > > cycles
    > > MISER_PLL_RESETN<='1';
    > > end if;
    > > if ( COUNT1 >= 100 ) THEN
    > > MISER_PLL_RESETN <='0';
    > > end if;
    > > if ( COUNT1 >= 150 ) THEN
    > > MISER_DSP_N <= '1';
    > > end if;
    > > end process;
    > >
    > > process ( MISER_DSP_N, COUNT1)
    > > begin
    > > -- enabling Clock Off
    > > if ( MISER_DSP_N = '1' ) THEN
    > > if ( COUNT1 >= 200 ) THEN
    > > MISER_CLKOFF <= '1';
    > > end if;
    > > if ( COUNT1 <= 250 ) THEN
    > > MISER_CLKOFF <= '0';
    > > end if;
    > >
    > > end if;
    > >
    > > end process;
    > >
    > > FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    > > '0' when ( MISER_CLKOFF = '1' ) else
    > > '0';
    > >
    > > FPGA_PLL_RESETN<= MISER_PLL_RESETN ;
    > > FPGA_DSP_N <= MISER_DSP_N ;
    > >
    > > end behavioral;
     
    Rama, Jan 17, 2007
    #7
  8. Rama

    Guest

    You have to handle two things here:

    (1) your code as-is is written outside of a process, using the
    when-else style assignment.
    (2) you want to convert a combinatorial decode into a synchronous one

    The usual solution will put your decoder into a process, and force you
    to use a sequential-style signal assignment, so no "when" condition
    (issue 1). Issue 2 means you have to decode the condition one clock
    early, so roll back your comparisons one value. Also, always remeber
    the reset, so if the combinatorial decode wold be false one clock after
    the counter is reset, so should your synchronous decode.

    The benefit is that your reset output will be clean, so no accidental
    glitches to spuriously reset the pll.

    Roughly, the basic process is:

    process (clk26mhz) is
    begin
    if rising_edge(clk26mhz) then
    if ((cnt_out >= 49) and (cnt_out <= 99)) and (reset /= '1') then
    MISER_PLL_RESETN <= '1';
    else
    MISER_PLL_RESETN <= '0';
    end if; -- selection
    end if; -- clk
    end process;

    - Kenn


    Rama wrote:
    > All,
    >
    > thank you so much. You have given me good insight about synthesis.
    > Yes you get locked into simulation mode TB's -- once you begin writing
    > sim TB's.
    >
    > I had one more question on how to write this equvalent synthesizable
    > code for this one statement -
    >
    > I had written a synchronous counter ( with synchronous reset internal
    > to the counter )
    >
    > count_test : count1 ( clk => CLK26MHZ,
    > reset => reset,
    > cntout => CNT_OUT );
    >
    > If I were to do this statement's equivalent code now --- How would I do
    > this in synthesis code of VHDL ? Any ideas/suggestions ?
    >
    > MISER_PLL_RESETN <= '1' when (CNT_OUT >= 50 and CNT_OUT <= 100) else
    > '0' ;
    >
    > Thanks much.
    >
    >
    > Andy wrote:
    > > Your code will generate a synchronous counter (good).
    > > But it will generate combinatorially decoded outputs (potentially bad;
    > > they will be glitchy).
    > >
    > > I would suggest you decode your outputs in the same process as the
    > > counter, so they will be synchronous (registered) too, and not have
    > > glitches which could cause problems elsewhere (especially if the resets
    > > are used asynchronously).
    > >
    > > Also, by coding everything in clocked process(es), you avoid the
    > > possibility of latches which are "a bad thing".
    > >
    > > Andy
    > >
    > >
    > > Rama wrote:
    > > > I have a question for the synthesis experts out there. I am a novice in
    > > > this area and am more of a functional verification person.
    > > >
    > > > However, here is a piece pf VHDL code - that i have and works fine in
    > > > the simulation world.
    > > >
    > > > However, when I program this same code onto thr FPGA - Xilinix ISE - I
    > > > don't see what I should be seeing ( was expecting the clock to turn off
    > > > )
    > > > The point of this piece of code was --
    > > > at time 0 --- have a default setup
    > > > wait for certain clock cycles -- reset the PLL
    > > > wait for some more clock cycles -- Reset the DSP
    > > > wait for some more clock cycles -- Then Shut the CLOCK off - the DSP
    > > > clock here.
    > > >
    > > > I tried doing the above -- in the code below.
    > > >
    > > > This works in the simulation -- I do see the expected result i.e
    > > >
    > > > I want to see the FPGA_MIZER_CLK - shut down after certain clock cycles
    > > > and after the DSP is reset. So i tried doing the sequence I need to
    > > > like this..
    > > >
    > > > The question is ----- Is this synthesizable ?
    > > >
    > > > What are the pitfalls ?
    > > >
    > > > (if you see I also have a counter and it is just counting
    > > > continuously....)
    > > >
    > > > I would like suggestions if there's different ways of doing the same
    > > > here.
    > > >
    > > > Thanks,
    > > > RC
    > > >
    > > > =============================
    > > >
    > > > I/O's declaration...
    > > >
    > > > FPGA_PLL_RESETN : out std_logic;
    > > > FPGA_PLL_SCLK : out std_logic;
    > > > FPGA_PLL_SCLK_SEL : out std_logic;
    > > > FPGA_MIZER_CLK : out std_logic;
    > > > FPGA_PLL_SIN : out std_logic;
    > > > FPGA_PLL_SEN : out std_logic;
    > > > FPGA_PLL_LD : out std_logic;
    > > >
    > > > FPGA_TRSTN : out std_logic;
    > > > FPGA_SCAN_EN : out std_logic;
    > > > FPGA_DSP_N : out std_logic;
    > > >
    > > > .....
    > > > .....CLK26MHZ : in std_logic;
    > > >
    > > >
    > > > architecture behavioral ...
    > > > begin
    > > > signal MISER_PLL_RESETN : std_logic := '0' ;
    > > > signal MIZER_CLK : std_logic := '0' ;
    > > > signal MISER_DSP_N : std_logic := '0';
    > > > signal MISER_CLKOFF : std_logic :='0';
    > > > signal COUNT1 : integer :=0;
    > > >
    > > > ...
    > > > ...
    > > > ..
    > > >
    > > > miser_control : process ( CLK26MHZ )
    > > > begin
    > > >
    > > > MIZER_CLK <= CLK26MHZ;
    > > > if rising_edge ( CLK26MHZ ) then
    > > > COUNT1 <= COUNT1 + 1 ; --- internal counter counting clk cycles
    > > > end if;
    > > >
    > > > end process;
    > > >
    > > > process ( COUNT1 )
    > > > begin
    > > > if ( COUNT1 >= 50 ) THEN -- e_pll_resetn - goes high after 50 clk
    > > > cycles
    > > > MISER_PLL_RESETN<='1';
    > > > end if;
    > > > if ( COUNT1 >= 100 ) THEN
    > > > MISER_PLL_RESETN <='0';
    > > > end if;
    > > > if ( COUNT1 >= 150 ) THEN
    > > > MISER_DSP_N <= '1';
    > > > end if;
    > > > end process;
    > > >
    > > > process ( MISER_DSP_N, COUNT1)
    > > > begin
    > > > -- enabling Clock Off
    > > > if ( MISER_DSP_N = '1' ) THEN
    > > > if ( COUNT1 >= 200 ) THEN
    > > > MISER_CLKOFF <= '1';
    > > > end if;
    > > > if ( COUNT1 <= 250 ) THEN
    > > > MISER_CLKOFF <= '0';
    > > > end if;
    > > >
    > > > end if;
    > > >
    > > > end process;
    > > >
    > > > FPGA_MIZER_CLK <= MIZER_CLK when ( MISER_CLKOFF = '0' ) else
    > > > '0' when ( MISER_CLKOFF = '1' ) else
    > > > '0';
    > > >
    > > > FPGA_PLL_RESETN<= MISER_PLL_RESETN ;
    > > > FPGA_DSP_N <= MISER_DSP_N ;
    > > >
    > > > end behavioral;
     
    , Jan 18, 2007
    #8
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