ISE 10.1 and Timing Simulation Errors

Discussion in 'VHDL' started by john, Feb 26, 2009.

  1. john

    john Guest

    Hi,

    I am trying to do the "Post Route Simulation" using ISE 10.1. Is "Post
    Route Simulation" same as " Timing Simulation"?

    The simulation "Post Place and Route Model" is giving me the following
    errors


    ERROR:HDLCompiler:377 - "ABC_TEST.vhd" Line 43. Entity port data_bus
    does not match with type unsigned of component port
    ERROR:HDLCompiler:377 - "ABC_TEST.vhd" Line 44. Entity port
    address_bus does not match with type unsigned of component port
    ERROR:HDLCompiler:377 - "ABC_TEST.vhd" Line 51. Entity port usb_data
    does not match with type unsigned of component port
    ERROR:HDLCompiler:377 - "ABC_TEST.vhd" Line 58. Entity port
    state_status does not match with type unsigned of component port
    ERROR:Simulator:777 - Static elaboration of top level VHDL design unit
    abc_test in library work failed



    The Test Bench Code is as follows

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;
    USE IEEE.STD_LOGIC_TEXTIO .ALL;

    ENTITY ABC_TEST IS
    END ABC_TEST;

    ARCHITECTURE behavior OF ABC_TEST IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DPR_Writer
    PORT(
    Data_Bus : OUT unsigned (13 downto 0);
    Address_bus : OUT unsigned (18 downto 0);
    Read_write : OUT std_logic;
    Output_Enable : OUT std_logic;
    CE0 : OUT std_logic;
    CE1 : OUT std_logic;
    LBL : OUT std_logic;
    UBL : OUT std_logic;
    USB_Data : IN unsigned (7 downto 0);
    USB_CLK : IN std_logic;
    ZZL : OUT std_logic;
    SEML : OUT std_logic;
    OPTL : IN std_logic;
    Reset : IN std_logic;
    Indicator_LED : OUT std_logic;
    State_status : out unsigned ( 1 downto 0)
    );
    END COMPONENT;


    --Inputs
    signal USB_Data :unsigned(7 downto 0) := (others => '0');
    signal USB_CLK : std_logic := '0';
    signal OPTL : std_logic := '0';
    signal Reset : std_logic := '0';

    --Outputs
    signal Data_Bus : unsigned(13 downto 0);
    signal Address_bus : unsigned(18 downto 0);
    signal Read_write : std_logic;
    signal Output_Enable : std_logic;
    signal CE0 : std_logic;
    signal CE1 : std_logic;
    signal LBL : std_logic;
    signal UBL : std_logic;
    signal ZZL : std_logic;
    signal SEML : std_logic;
    signal Indicator_LED : std_logic;
    signal State_status : unsigned ( 1 downto 0);
    constant USB_CLK_period : time := 42 ns;

    BEGIN
    -- Instantiate the Unit Under Test (UUT)
    uut: DPR_Writer PORT MAP (
    Data_Bus => Data_Bus,
    Address_bus => Address_bus,
    Read_write => Read_write,
    Output_Enable => Output_Enable,
    CE0 => CE0,
    CE1 => CE1,
    LBL => LBL,
    UBL => UBL,
    USB_Data => USB_Data,
    USB_CLK => USB_CLK,
    ZZL => ZZL,
    SEML => SEML,
    OPTL => OPTL,
    Reset => Reset,
    Indicator_LED => Indicator_LED,
    State_status => State_status
    );

    -------------------------------------------------
    USB_CLK_process :process
    begin
    USB_CLK<= '0';
    wait for USB_CLK_period/2;
    USB_CLK <= '1';
    wait for USB_CLK_period/2;
    end process;
    -----------------------------------------------

    -- Stimulus process
    stim_proc: process
    begin
    -- hold reset state for 100ms.
    wait for 100ms;
    wait for USB_CLK_period*10;
    -- insert stimulus here
    wait;
    end process;

    -------------------------------------------------

    Reset_Process: Process
    Begin
    Reset <= '1';
    wait for 100 ns;
    Reset <='0';
    wait for 6000 ns;
    End Process;

    -----------------------------------------------
    USB_Data_Stream: Process
    Begin
    USB_Data(0)<= '0';
    USB_Data(1)<='1' ;
    USB_Data(2)<= '0';
    USB_Data(3)<= '1';
    USB_Data(4)<= '0';
    USB_Data(5)<= '1';
    USB_Data(6)<= '0';
    USB_Data(7)<= '1';
    wait for 100 ns;
    USB_Data(0)<= '1';
    USB_Data(1)<='0' ;
    USB_Data(2)<= '1';
    USB_Data(3)<= '0';
    USB_Data(4)<= '1';
    USB_Data(5)<= '0';
    USB_Data(6)<= '1';
    USB_Data(7)<= '0';
    wait for 100 ns;
    end process;
    ---------------------------------------------
    END behavior;


    And the VHDL Code is as follows

    Library IEEE;
    USE IEEE.Std_logic_1164 .ALL;
    USE IEEE.Numeric_std .ALL;
    USE IEEE.STD_LOGIC_TEXTIO .ALL;

    Entity DPR_Writer is
    port (

    Data_Bus : out unsigned (13 downto 0 );
    Address_bus : out unsigned (18 downto 0 );
    Read_write : out std_logic;
    Output_Enable : out
    std_logic;
    CE0 : out std_logic;
    CE1 : out std_logic;
    LBL : out std_logic;
    UBL : out std_logic;
    USB_Data : in unsigned (7 downto 0 );
    USB_CLK : in std_logic;
    ZZL : out std_logic:='0';
    SEML : out std_logic;
    OPTL : in std_logic;
    Reset : in std_logic;
    Indicator_LED : out std_logic;
    State_status : out unsigned ( 1 downto 0)
    );
    End DPR_Writer;

    Architecture Writer of DPR_Writer is

    Signal State : unsigned(1 downto 0);
    Signal Next_State : unsigned(1 downto 0);
    Constant G0 : unsigned(1 downto 0):="00";
    Constant G1 : unsigned(1 downto 0):="01";
    Constant G2 : unsigned(1 downto 0):="10";
    Constant G3 : unsigned(1 downto 0):="11";
    Signal Incr : std_logic;
    Signal Stop : std_logic;
    Signal Counter : unsigned ( 18 downto 0);
    Signal Ld_high : std_logic;
    Signal Ld_Low : std_logic;
    Signal Reset_out : std_logic;
    Signal incr_out : std_logic;
    Signal Ld_high_out : std_logic;
    Signal Ld_Low_out : std_logic;
    ------------------------------------

    Begin

    --CE0 <= '0';
    --CE1 <= '1';
    CE0 <= Ld_high;
    CE1 <= Ld_Low;
    Output_Enable <= '1';
    Read_write <= '0';
    SEML <=Reset_out;
    Address_bus <= Counter;
    ZZL <= incr ;
    State_status <= State;

    -------------------------------------

    State_Machine: Process (State)
    Begin
    Case State is

    When G0=>
    Ld_high <= '1';
    Ld_Low <= '0';
    --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    UBL <='0'; --1 old value
    LBL <='0'; --0 0ld value
    Next_State <=G1;
    -- Address Bus did not change

    When G1 =>
    Incr <='0';
    Ld_high <= '0';
    Ld_Low <= '1';
    --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    UBL <='0'; --0 old value
    LBL <='0'; --1 old value
    Next_State <=G2;
    -- Address Bus did not change

    When G2 =>
    Incr <='1';
    Ld_high <= '1';
    Ld_Low <= '0';
    --Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    ---- Data_Bus ( 5 downto 0) <= USB_Data ( 5 downto 0 );
    UBL <='0';
    LBL <='0';
    Next_State <=G3;
    -- Address Bus changes

    When G3 =>
    Incr <='0';
    Ld_high <= '0';
    Ld_Low <= '1';
    --Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    ---- Data_Bus ( 13 downto 6) <= USB_Data ( 7 downto 0 );
    UBL <='0';
    LBL <='0';
    Next_State <=G2;
    -- Address Bus did not change

    When others =>
    Next_State <=G0;
    End case;
    End Process;
    ----------------------------------------
    FSM : Process (USB_CLK,Reset_out)
    Begin

    If ( Reset_out= '1' ) Then
    Indicator_LED <= '1';
    State <= G0;
    elsIf (USB_CLK 'Event And USB_CLK = '1')Then
    Indicator_LED <= '0';
    State <= Next_State;
    End If;

    End Process;
    ----------------------------------------
    Count: Process ( USB_CLK,Reset_out, incr)
    Begin
    If ( Reset_out= '1' ) Then
    Counter <= (others => '0');

    elsif (USB_CLK 'Event And USB_CLK = '1')Then
    If ( Counter = 255008 )Then
    -- Counter will stop counting --
    elsif ( Incr = '1') then
    Counter <= Counter + 1;
    else
    Counter <= Counter;
    End if;
    End if;
    End Process;
    ----------------------------------------
    Data_Bus_Load: Process( USB_CLK, Ld_high, Ld_Low,Reset_out)
    Begin

    If ( Reset_out= '1' ) Then
    Data_Bus ( 13 downto 8) <=(others =>'0');
    Data_Bus ( 7 downto 0) <=(others =>'0');

    elsif (USB_CLK = '1')Then

    If ( Ld_high = '1' ) Then
    Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
    elsif (Ld_Low ='1') then
    Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
    elsif ( Ld_high = '0' ) Then
    elsif(Ld_Low ='0') then
    else
    end if;

    else
    end if;

    End Process;
    ----------------------------------------
    Reset_Scheme : Process( USB_CLK, Reset)
    variable Reset_in : std_logic;
    variable Reset_out_1 :std_logic;
    Begin
    If ( Reset = '1') then
    Reset_in := '1';
    Reset_out_1 := '1';
    Elsif rising_edge ( USB_CLK ) then
    Reset_out_1 := Reset_in;
    Reset_in :='0';
    End if ;
    Reset_out <= Reset_out_1;
    End Process;


    Regards,

    John
     
    john, Feb 26, 2009
    #1
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  2. john

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    Did you recently change the component definition? The types in the test bench appear correct, so ISE may be pulling some old data out of a queue and getting confused. Select <Project><Cleanup project files> from the toolbar and they try running your post route sim again. This will regenerate the entire project from scratch.

    My menu selection is from ISE8.2, I believe that is the same in 10.1 but I don't have that running at the moment.

    John
     
    Last edited: Feb 26, 2009
    JohnDuq, Feb 26, 2009
    #2
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  3. john

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    The problem is that, for synthesizing, Xilinx assumes every port is either of type std_logic or std_logic_vector (as it generates a new VHDL file that executed the synthesized model, including precise timing simulation)
    In order for it to work with a synthesizer, you should change the entity definition such that it'll look like this:

    Code:
    Entity 	DPR_Writer	is
    port (
    
    Data_Bus 				:  out 		std_logic_vector(13 downto 0 );
    Address_bus 		:  out		std_logic_vector(18 downto 0 );
    Read_write			:  out 		std_logic;
    Output_Enable :	  out
    std_logic;
    CE0								:  out 		std_logic;
    CE1 							: 	out 		std_logic;
    LBL 								: 	out 		std_logic;
    UBL 							: 	out 		std_logic;
    USB_Data 				:		in	 		std_logic_vector(7 downto 0 );
    USB_CLK 				: 	in 		  std_logic;
    ZZL								: 	out		std_logic:='0';
    SEML							: 	out		std_logic;
    OPTL 							: 	in 		  std_logic;
    Reset							:		in 		  std_logic;
    Indicator_LED		:	  out		std_logic;
    State_status     :   out    std_logic_vector( 1 downto 0)
    );
    End DPR_Writer;
    In the architecture you are free to use whatever types you prefer as long as the ports are all std_logic/std_logic_vector.
     
    Last edited: Feb 26, 2009
    joris, Feb 26, 2009
    #3
  4. john

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    Nice catch, Joris! I hadn't run into that little quirk yet.
     
    JohnDuq, Feb 26, 2009
    #4
  5. john

    Tricky Guest

    I can see some problems in your DPR writer declaration - Im assuming
    this is the design to be place and routed:

    > Count: Process ( USB_CLK,Reset_out, incr)


    you only need USB_CLK and reset_out in the sensitivity list. not a
    problem, but in rtl simulation you're making the simulator work harder
    than it needs to.

    > Data_Bus_Load: Process( USB_CLK, Ld_high, Ld_Low,Reset_out)


    from the way you have defined the process, you have missed USB_Data
    from the sensitivity list. this means you will not be simulating
    properly as you have set usb_clock up as an enable in logic. But this
    is the main problem - you are using your clock in logic. it is not
    recommended to do this as even though it may work in rtl simulation,
    you are likely to violate plenty of setup and hold times on the actual
    chip. use it as a clock instead of a gated signal.
     
    Tricky, Feb 27, 2009
    #5
  6. john

    john Guest

    Hi,

    I want to Program the spartan chip and thought the timing analysis
    will give me more information about my code. But is it true? , that
    Can I use "Timing Simulation" to

    1. Confirm my VHDL code for FPGA Programming.

    2. Confirm my VHDL design, if I want to make a Chip out of it.

    Thanks

    John
     
    john, Feb 27, 2009
    #6
  7. john

    Tricky Guest

    On Feb 27, 3:11 pm, john <> wrote:
    > Hi,
    >
    > I want to Program the spartan chip and thought the timing analysis
    > will give me more information about my code. But is it true? ,  that
    > Can I use "Timing Simulation" to
    >
    > 1. Confirm my VHDL code for FPGA Programming.
    >
    > 2. Confirm my VHDL design, if I want to make a Chip out of it.
    >
    > Thanks
    >
    > John


    you dont need to do a timing simlation to do that. The best thing to
    do is just to simulate the raw VHDL. its much quicker, and most of the
    time, correct VHDL will result in working synthesized code.
     
    Tricky, Feb 27, 2009
    #7
  8. john

    john Guest

    So, you are saying that "Behavorial Simulation" is enough to Test the
    VHDL code for FPGA Programming and Chip Designing. But does "Timing
    Simulation" gives information about Setup and hold timing voilations.

    Thanks
    John
     
    john, Feb 27, 2009
    #8
  9. john

    Tricky Guest

    On Feb 27, 3:31 pm, john <> wrote:
    > So,  you are saying that "Behavorial Simulation" is enough to Test the
    > VHDL code for FPGA Programming and Chip Designing. But does "Timing
    > Simulation" gives information about Setup and hold timing voilations.
    >
    > Thanks
    > John


    behavioral simulation will take you if the VHDL behaves as you
    intended, but it will only behave as you instruct. The sensitivity
    list problems I pointed out above will NOT show up, but then your
    placed and routed design will not behave like you intended.

    running the timing analyser, with suffienct timing information, will
    tell you if you're violating set up and hold times over a P&R'ed
    design.
     
    Tricky, Feb 27, 2009
    #9
  10. john

    john Guest

    Hi,

    What does P&R'ed mean ? So, both behavorial and timing simulaion are
    important to program a FPGA? Am I right?

    John
     
    john, Feb 27, 2009
    #10
  11. john

    Tricky Guest

    On Feb 27, 4:26 pm, john <> wrote:
    > Hi,
    >
    > What does P&R'ed mean ? So, both behavorial and timing simulaion are
    > important to program a FPGA? Am I right?
    >
    > John


    P&R'ed = place and routed.

    you technically dont need to do either. but its a good idea that you
    do.
     
    Tricky, Feb 27, 2009
    #11
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