latch inferrence in clocked process

Discussion in 'VHDL' started by vu, Aug 9, 2006.

  1. vu

    vu Guest

    Hello,

    I am a beginner to VHDL and new to this forum, and I hope someone could
    give me a hand with this question.

    Can a latch be inferred in a process that has clk in the sensitivity
    list? If no, then does this mean the if statement does not require and
    else statement to match it? Something along the lines of :

    .....
    process(clk) is
    begin
    if (rising_edge(clk)) then
    if (a = '1') then b<= '0'
    end if;
    end process;
    .....
     
    vu, Aug 9, 2006
    #1
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  2. "vu" <> writes:

    > Hello,
    >
    > I am a beginner to VHDL and new to this forum, and I hope someone could
    > give me a hand with this question.
    >
    > Can a latch be inferred in a process that has clk in the sensitivity
    > list?


    Yes. The following code will infer a latch for q(1) in Synopsys DC (at
    least last time I 'tried'):

    architecture rtl of example is
    signal q : std_logic_vector(1 downto 0);
    begin
    process (reset, clk) is
    begin
    if reset = '0' then
    q <= (others => '0');
    elsif rising_edge(clk) then
    if ena = '1' then
    q(0) <= d;
    end if;
    end if;
    end process;
    end rtl;

    > If no, then does this mean the if statement does not require and
    > else statement to match it? Something along the lines of :

    (snip)

    If you don't have an else cause, the effectively create a flop with an
    enable bit - see the code snippet above which will infer an FF with an
    enable bit for q(0).


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
     
    Kai Harrekilde-Petersen, Aug 9, 2006
    #2
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  3. vu wrote:

    > Can a latch be inferred in a process that has clk in the sensitivity
    > list?


    no
    A synchronous "latch" is a d-flop.

    > If no, then does this mean the if statement does not require and
    > else statement to match it?


    yes

    >Something along the lines of :
    >
    > ....
    > process(clk) is
    > begin
    > if (rising_edge(clk)) then
    > if (a = '1') then b<= '0'
    > end if;
    > end process;
    > ....


    Once you fix the syntax errors,
    your example would latch low forever
    when A goes high. But since an fpga
    registers start low on configuration,
    synthesis would likely just wire
    B to ground for you.

    A more interesting example would give
    the output some way to recover.

    For a synchronous design, think about
    how you want your registers to
    initialize and update Describe that
    exactly, and don't worry about what
    synthesis will do.


    -- Mike Treseler

    ____________________________
    library ieee;
    use ieee.std_logic_1164.all;
    entity no_else is
    port (a, clk : in std_ulogic;
    b : out std_ulogic);
    end no_else;

    architecture sim of no_else is
    begin
    process(clk) is
    begin
    ck : if (rising_edge(clk)) then
    b <= a;
    if (a = '1') then
    b <= '1';
    end if;
    end if ck;
    end process;
    end architecture;
     
    Mike Treseler, Aug 9, 2006
    #3
  4. vu

    arant

    Joined:
    Aug 14, 2006
    Messages:
    2
    > Can a latch be inferred in a process that has clk in the sensitivity
    > list?

    One situation that I can think of is for a clock gate block like this

    entity clk_gate_cell
    port (
    clk , enable : in std_logic;
    clk_out : out std_logic);
    end clk_gate_cell;

    architecture str of clk_gate_cell is
    begin
    --- combo logic for clk gating
    --- pass clock only when enable = '1'
    p_clkgate : process(clk,enable)
    begin
    if (enable = '1') then
    clk_out <= clk;
    else
    clk_out <= '0';
    end if;
    end process p_clkgate;
    end str;

    if the italicised portion is left out then a latch will be inferred even when clock is there in the sentivity list ... ok I agree we never use clock gating like this in real SoCs but hey what the heck
     
    arant, Aug 14, 2006
    #4
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