Latch problem in FSM

[engrjet]

Hi
I'm facing a problem in latching data inside the state of an FSM.
If I latch it in any of the state and read it out side the process I read it wrongly but if I directly latch it out side the process I read it correctly.
what may be the reason. what will be the solution for this???

please reply
Thank You

 

[jeppe]

Try Evita VHDL handbook from Aldec.Com specially chapter 6