Latch problem in FSM

Discussion in 'VHDL' started by engrjet, Mar 12, 2008.

  1. engrjet

    engrjet

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    Hi
    I'm facing a problem in latching data inside the state of an FSM.
    If I latch it in any of the state and read it out side the process I read it wrongly but if I directly latch it out side the process I read it correctly.
    what may be the reason. what will be the solution for this???

    please reply
    Thank You
     
    engrjet, Mar 12, 2008
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  2. engrjet

    jeppe

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    Try Evita VHDL handbook from Aldec.Com specially chapter 6
     
    Last edited: Mar 13, 2008
    jeppe, Mar 13, 2008
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