Hi, VHDL novice here. I have designed a simple cache using Xilinx ISE 8.2i. Whilst attempting to simulate the design ModelSim complained that a function in a package is used to set a constant before the function is defined (although it had been declared and was defined in the same file). So I attempted so solve the problem by making a second package (previously there was only a single package) containing the constant declarations while the functions remained in the first package. However, it now won't synthesise and ModelSim won't work either. This is because the system doesn't recognise my second package. It always seems to associate it with the first no matter how many times I remove the packages and re-add them. Sometimes I get an error saying that the first package is defined by two different files (the second of which corresponds to my new package). I'm really not sure what to do and the online help is no good. Any ideas? Thanks in advance.