LRM guru question

Discussion in 'VHDL' started by Jonathan Bromley, Oct 30, 2003.

  1. Hi all,

    Normally I reckon that I know my way around VHDL pretty well.
    This one, however, has me stumped. I expect it's in the
    LRM - most things are :) - but I can't find it.
    Clarification welcome...

    Suppose I have an entity and (to keep things simple) a
    matching component declaration, and it has an unconstrained
    array output port...

    entity E is port (P: out bit_vector); end;

    Now, if I instance it in an architecture, the unconstrained
    array port is of course constrained to have the same subtype
    as the signal connected to it...

    ....
    signal V: bit_vector(2 downto 0);
    ....
    inst: E port map (P => V);
    -- port P is now constrained (2 downto 0) like V

    However, suppose I now apply a conversion function to that
    output port...

    ....
    signal W: widget;
    function F(BV: in bit_vector) return widget is...
    ....
    inst: E port map (F(P) => W);

    Since the unconstrained port is an *input* to the
    conversion function, how does it get its subtype constraint?
    Or is this illegal? Illegal sounds likely, but where is this
    defined in the LRM?

    Thanks in advance
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Oct 30, 2003
    #1
    1. Advertising

  2. Hi,

    I'm no guru, but perhaps this is what you are looking for
    (cited from LRM Section 3.2.1.1 "Index constraints and discrete
    ranges"):

    "If the index ranges for an interface object or member of
    an interface object are obtained from the corresponding
    association element (when associating in whole) or elements
    (when associating individually), then they are determined
    either by the actual part(s) or by the formal part(s) of
    the association element(s), depending upon the mode of the
    interface object, as follows:

    ...

    - For an interface object or member of an interface
    object whose mode is out, buffer, inout, or
    linkage, if the formal part includes a conversion
    function or a type conversion, then the parameter
    subtype of that function or the type mark of the
    type conversion must be a constrained array subtype,
    and the index ranges are obtained from this constrained
    subtype; otherwise, the index ranges are obtained from
    the object denoted by the actual designator(s)."

    --
    Edwin



    Jonathan Bromley wrote:
    > Hi all,
    >
    > Normally I reckon that I know my way around VHDL pretty well.
    > This one, however, has me stumped. I expect it's in the
    > LRM - most things are :) - but I can't find it.
    > Clarification welcome...
    >
    > Suppose I have an entity and (to keep things simple) a
    > matching component declaration, and it has an unconstrained
    > array output port...
    >
    > entity E is port (P: out bit_vector); end;
    >
    > Now, if I instance it in an architecture, the unconstrained
    > array port is of course constrained to have the same subtype
    > as the signal connected to it...
    >
    > ...
    > signal V: bit_vector(2 downto 0);
    > ...
    > inst: E port map (P => V);
    > -- port P is now constrained (2 downto 0) like V
    >
    > However, suppose I now apply a conversion function to that
    > output port...
    >
    > ...
    > signal W: widget;
    > function F(BV: in bit_vector) return widget is...
    > ...
    > inst: E port map (F(P) => W);
    >
    > Since the unconstrained port is an *input* to the
    > conversion function, how does it get its subtype constraint?
    > Or is this illegal? Illegal sounds likely, but where is this
    > defined in the LRM?
    >
    > Thanks in advance
    > --
    > Jonathan Bromley, Consultant
    >
    > DOULOS - Developing Design Know-how
    > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
    >
    > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    > Tel: +44 (0)1425 471223 mail:
    > Fax: +44 (0)1425 471573 Web: http://www.doulos.com
    >
    > The contents of this message may contain personal views which
    > are not the views of Doulos Ltd., unless specifically stated.
    >
    >
    >
    Edwin Naroska, Oct 30, 2003
    #2
    1. Advertising

  3. "Edwin Naroska" <-technik.uni-dortmund.de> wrote
    in message news:-technik.uni-dortmund.de...

    > (cited from LRM Section 3.2.1.1 "Index constraints and discrete
    > ranges"):

    [...]
    > if the formal part includes a conversion
    > function or a type conversion, then the parameter
    > subtype of that function or the type mark of the
    > type conversion must be a constrained array subtype,
    > and the index ranges are obtained from this constrained
    > subtype


    Bulls-eye! Thanks very much.
    --

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:
    Fax: +44 (0)1425 471573 Web: http://www.doulos.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Oct 30, 2003
    #3
  4. Jonathan Bromley

    Deb P Guest

    "Jonathan Bromley" <> wrote in message news:<b
    <snip>

    > Since the unconstrained port is an *input* to the
    > conversion function, how does it get its subtype constraint?
    > Or is this illegal? Illegal sounds likely, but where is this
    > defined in the LRM?
    >


    This is legal VHDL. Not sure how many simulators support this correctly though ;)
    Deb P, Oct 31, 2003
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. jamesu

    for you LRM gurus

    jamesu, Oct 23, 2003, in forum: VHDL
    Replies:
    1
    Views:
    488
    Edwin Naroska
    Oct 24, 2003
  2. Colby L. Canutt

    Need help finding LRM Draft

    Colby L. Canutt, Sep 3, 2004, in forum: VHDL
    Replies:
    0
    Views:
    441
    Colby L. Canutt
    Sep 3, 2004
  3. yaveh (Yet Another Vhdl Engineer Hoping)

    RFC on VHDL LRM 93[8.4.1]

    yaveh (Yet Another Vhdl Engineer Hoping), Oct 17, 2006, in forum: VHDL
    Replies:
    22
    Views:
    1,261
  4. Amal

    Accellera VHDL 2006 LRM

    Amal, Jun 15, 2007, in forum: VHDL
    Replies:
    7
    Views:
    550
    David Bishop
    Jun 20, 2007
  5. KJ
    Replies:
    2
    Views:
    611
Loading...

Share This Page