Map net into BRAM

[SmiG]

Hi guys,

I'm writing from italy and I have some problems with read/write data
accross on array of std_logic_vector.

Declaration of these signals is the following:

###
type array_8bit is array (127 downto 0) of std_logic_vector(7 downto 0);
signal amp_pg : array_8bit;

..
..
..
..
LOCAL_AMP_PG <= amp_pg(conv_integer(num_chain_s3));
###


I would map this kind of signal into a BRAM and not into a FF.
Is it possible?
If yes there is a inline attribute to be set on the signal declaration?


I'm using XST trougth Xilinx EDK tool,

Thanks in advance,

SmiG

 

[Weng Tianxiang]

Hi,
BRAM behaviors are different from FF. You must use CoreGenerate to
produce BRAM block to get the right operations.

For example, when the first data is written to BRAM, its output will
appear on output port after 1 clock delays, not as the 2nd clock as FF
does.

Weng

 

[radarman]

I think you have that backwards.

If you instantiate an array in FF's, read data can be made available on
the same clock, if you can tolerate a fairly long combinational delay.
I implement these all the time when I need a small register bank for
something.

BRAM's, on the other hand, are fully synchronous dual-port RAM's
sitting on the die. Thus, it takes one clock to get the data into the
RAM array, and another clock to get it out. There may be some
exceptions that will allow data to flow through in one clock, but I
can't think of any off the top of my head.

The posters problem is that the structure doesn't look like a RAM. A
RAM requires some form of storage, or latching. I posted a dual-port
RAM model in another post that demostrates how to infer a sync-write,
async-read RAM model with pure VHDL constructs. If not, email me and I
can send you a copy separately.