metastability

[fabbl]

Chris,
To do this the tool would have to create timing paths, redundant to what
synthesis and PAR tools do. What you really need to do is design your code
with fan-out and delay in mind. Timing reports from PAR and synthesis
provide visibility into timing issues (most of the time) and will be more
reliable than something second guessing your design from a design entry
point of view.

 

[Chris]

Do any programs exist which can analyze VHDL code and predict any problems
with metastability?

 

[Marcus Harnisch]

Do any programs exist which can analyze VHDL code and predict any problems
with metastability?

Novas' nLint comes to mind. It checks whether registers in different
clock domains are connected back-to-back and reports a violation if it
could find any of the common synchronizer structures. You can also
tell it about your own synchronizer modules, which will then be looked
for. That's to cover the most common case.

Best regards,
Marcus

 

[VhdlCohen]

Novas' nLint comes to mind. It checks whether registers in different
clock domains are connected back-to-back and reports a violation if it
could find any of the common synchronizer structures. You can also
tell it about your own synchronizer modules, which will then be looked
for. That's to cover the most common case.

@HDL also provides a similar product.
http://www.athdl.com/pdf/Clock_Domain_Datasheet.pdf

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* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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[Marcus Harnisch]

Novas' nLint comes to mind. It checks whether registers in different
clock domains are connected back-to-back and reports a violation if it
could find any of the common synchronizer structures.

^^^^^
could not

I sure you got that, but still...

 

[Jos De Laender]

Do any programs exist which can analyze VHDL code and predict any problems
with metastability?

Guess you should be a bit more specific on what you mean ...

Do you really mean 'metastability' ? This being a physical phenomenon ,
there's no way to predict this on the VHDL (logical) level.

Or are you referring to - as other posters are interpreting it - predicting
trouble because I was sloppy in synchronizing ? There all major EDA vendors
have something in their portfolio to help you ...

 

[fabbl]

I'd like to add that I don't think it is a good idea to try to predict
place/route results at the logical level. Think about how a tool would have
to do this. It's best to read STA reports and design with timing in mind.
I'm sure the market may see the demand for a tool and try to fill it, I'm
skeptical as to the trustworthiness of the results.