metastability

Discussion in 'VHDL' started by fabbl, Jan 16, 2004.

  1. fabbl

    fabbl Guest

    Chris,
    To do this the tool would have to create timing paths, redundant to what
    synthesis and PAR tools do. What you really need to do is design your code
    with fan-out and delay in mind. Timing reports from PAR and synthesis
    provide visibility into timing issues (most of the time) and will be more
    reliable than something second guessing your design from a design entry
    point of view.



    "Chris" <> wrote in message
    news:bu8qas$v0k$...
    > Do any programs exist which can analyze VHDL code and predict any problems
    > with metastability?
    >
    >
    fabbl, Jan 16, 2004
    #1
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  2. fabbl

    Chris Guest

    Do any programs exist which can analyze VHDL code and predict any problems
    with metastability?
    Chris, Jan 16, 2004
    #2
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  3. "Chris" <> writes:
    > Do any programs exist which can analyze VHDL code and predict any problems
    > with metastability?


    Novas' nLint comes to mind. It checks whether registers in different
    clock domains are connected back-to-back and reports a violation if it
    could find any of the common synchronizer structures. You can also
    tell it about your own synchronizer modules, which will then be looked
    for. That's to cover the most common case.

    Best regards,
    Marcus

    --
    Marcus Harnisch | Mint Technology, a division of LSI Logic
    | 200 West Street, Waltham, MA 02431
    Tel: +1-781-768-0772 | http://www.lsilogic.com
    Marcus Harnisch, Jan 16, 2004
    #3
  4. fabbl

    VhdlCohen Guest

    >"Chris" <> writes:
    >> Do any programs exist which can analyze VHDL code and predict any problems
    >> with metastability?

    >
    >Novas' nLint comes to mind. It checks whether registers in different
    >clock domains are connected back-to-back and reports a violation if it
    >could find any of the common synchronizer structures. You can also
    >tell it about your own synchronizer modules, which will then be looked
    >for. That's to cover the most common case.
    >


    @HDL also provides a similar product.
    http://www.athdl.com/pdf/Clock_Domain_Datasheet.pdf

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    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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    VhdlCohen, Jan 17, 2004
    #4
  5. Marcus Harnisch <> writes:
    > Novas' nLint comes to mind. It checks whether registers in different
    > clock domains are connected back-to-back and reports a violation if it
    > could find any of the common synchronizer structures.

    ^^^^^
    could not

    I sure you got that, but still...

    --
    Marcus Harnisch | Mint Technology, a division of LSI Logic
    | 200 West Street, Waltham, MA 02431
    Tel: +1-781-768-0772 | http://www.lsilogic.com
    Marcus Harnisch, Jan 19, 2004
    #5
  6. Chris wrote:

    > Do any programs exist which can analyze VHDL code and predict any problems
    > with metastability?


    Guess you should be a bit more specific on what you mean ...

    Do you really mean 'metastability' ? This being a physical phenomenon ,
    there's no way to predict this on the VHDL (logical) level.

    Or are you referring to - as other posters are interpreting it - predicting
    trouble because I was sloppy in synchronizing ? There all major EDA vendors
    have something in their portfolio to help you ...

    --
    Jos De Laender
    Jos De Laender, Jan 19, 2004
    #6
  7. fabbl

    fabbl Guest

    I'd like to add that I don't think it is a good idea to try to predict
    place/route results at the logical level. Think about how a tool would have
    to do this. It's best to read STA reports and design with timing in mind.
    I'm sure the market may see the demand for a tool and try to fill it, I'm
    skeptical as to the trustworthiness of the results.
    fabbl, Jan 20, 2004
    #7
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