Modelsim "Cannot read output"

[Ardni]

Hi all,
I am having a problem with Modelsim while trying to do a timing simulation. I saw a similar question asked some time ago but I think this may be a different issue.

I have inserted a PLL to which converts a 40MHz input to 83MHz which is used to clock a serial interface. The design works on the board, but when I try to do a timing simulation with Modelsim (Version 6.2d) I get the following error "Cannot read output "a_clk0"."

I am using the output of the PLL to clock the logic of a serial interface, it is later sent as an output clock for the interface, but is copied to a signal beforehand, so does not go directly to an output pin of the FPGA. I am aware that I cannot read outputs but as this is an internal signal, I am confused as to why Modelsim is complaining.

I have seen this problem before when I was writting code for a reset module. I passed the reset signal which came from outside through 2 flips flops and then used the delayed signal to do the reset. I read this was good practice, but anyway Modelsim complained when i did this, but only sometimes, for certain modules. I never could understand it so i just got rid of the 2 flip flops so Modelsim wouldn´t complain. However after seeing this issue again, I thin it´s time for me to understand it. I am hoping someone out there knows why.
I´d be so grateful if anyone has a solution.

By the way, I am using:
Stratix 2 GX FPGA
Quartus II 7.1
Modelsim 6.2d

Many thanks for your help.

 

[Ardni]

Hi again,
I haven´t yet found a solution to this problem, but I have noticed something when looking at the compilation result in quartus. The output of the PLL in question which clocks the logic to implement a serial interface does not appear in the results for the 'clock setup' and 'clock hold' headings.
I have another PLL which does a similar job, but it appears in the timing results and causes no problems with Modelsim.
The only difference in the PLL´s is that one is a Fast PLL and the one which is giving the problem is an Enhanced PLL. I don´t know if that would make a difference.

Does anybody have any ideas as to why the results for one of the clocks would not appear in the timing results and then cause problems in Modelsim later?

Thanks for any help

 

[Ardni]

Also, I forgot to say that I dont have any warnings reagarding the PLL and quartus tells me that it was implemented as an enhanced PLL successfully.

Also its seems to work on the board. i.e. the clock (o/p of the PLL) is outputted on a serial interface and it also clocks the logic for the data to be sent, everything seems to function correctly at the FPGA outputs, but I still dont understand why I see the above 2 issues.

Thanks

 

[Ardni]

Apologies, please igonore my above comments regarding the clock results not appearing in the timing reults. I made various changes to the program in an attempt to understand why I might have this problem with modelsim and I didn´t realise that this clock was not being used and therefore did not appear in the results.

Anyway it seems I still have the issue with Modelsim, if anybody has any ideas I´d be really grateful. I find myself changing many things that I don´t understand 100%. For example why a Fast PLL works but a Enchanced PLL doesn´t

Many thanks.